ESD--Silicon on Insulator (SOI) ESD Design

1. SOI ESD BASIC CONCEPTS

SOI ESD design is distinct from bulk CMOS ESD design as a result of the buried oxide (BOX) film and the MOSFET floating body region. The BOX decouples the SOI n- and p-channel MOSFET body region from the silicon substrate. The BOX region also separates and isolates the p- and n-channel SOI MOSFET. Many of the bulk ESD design practices are similar, but new issues need to be addressed in SOI ESD design. In SOI ESD analysis, active areas include SOI electro-thermal simulation and modeling, experimental work and design integration, and SOI patents.

Although many of the basic concepts of ESD design in SOI and bulk CMOS technology are similar, the actual physical layout of the structures and ESD network integration can be significantly different. This has led to the need for new semiconductor devices, new ESD design layout, and new circuit innovations.

Some of the fundamental distinctions are as follows:

_ No vertical parasitic devices exist.

_ No lateral device exists without formation of a MOSFET gate structure; hence, SOI MOSFETs, diodes, and resistors utilize gate structures.

_ Vertical shallow trench isolation (STI)-bound p+ anode/n-well cathode diode structure does not exist in SOI technology.

_ n-well-to-substrate ESD diode elements do not exist in SOI technology.

_ Parasitic CMOS-based pnpn structures do not exist in SOI technology.

_ There are no vertical diode elements, hence no advantage to the area dependency in the design of structures.

_ There are no guard ring structures needed in SOI technology.

_ There are no local substrate contact guard rings for SOI devices.

_ n- and p-well regions do not exist.

_ Bulk ''floating gate tie-downs'' and well tie-downs do not exist.

_ Unique electrical connections need to be established with the substrate region in SOI technology.

As a result of the above issues, although the basic concepts in SOI ESD design are the same, there are significant differences in the physical layout and device choices. Additionally, even with the direct mapping of circuits, the ESD response circuit can be significantly different, leading to new ESD issues and failure mechanisms.

Where at first glance, the presence of the BOX appears to be a serious decrement to SOI ESD design, the issues above can lead to significant advantages over bulk CMOS silicon ESD design.

The lack of vertical parasitic devices leads to a reduction of the complexity of device-to device interactions. In bulk CMOS, a significant number of ESD failures and concerns are unanticipated interactions between adjacent elements and adjacent circuits; in SOI, this is not true. In bulk CMOS ESD design, the interaction between adjacent elements and circuits leads to complex ESD design rules and logical-to-physical checking computer-aided design (CAD) tools. In SOI, ESD design is significantly simplified because of the elimination of these unexpected interactions and current paths. This simplifies the ESD analysis and prevents undesired interaction.

SOI ESD design will be dependent on library elements and supported structures not parasitic elements, which are not well quantified. In technology development, the parasitic model elements are used, which are not well defined and do not have electrical models.

Additionally, they are not present in the schematic design. As a result, the awareness and predictability of ESD results are hampered. In bulk CMOS technology, these limited the prediction and projection capability of ESD robustness of products. Hence, the elimination of bulk CMOS parasitic device interaction has significantly assisted the predictive capability and assurance of SOI ESD results.

The lack of parasitic transistors and the physical isolation of the structures also eliminate the traditional CMOS latchup observed in bulk CMOS technology. This is because there are no parasitic vertical or lateral pnp and npn elements. In bulk CMOS, the parasitic pnp bipolar transistor pnp base and collector are formed from the n-well and substrate, respectively. The parasitic npn bipolar transistor base and collector are formed from the substrate and the n-well, respectively. These parasitic transistors share the same physical regions, and are cross-coupled forming a Shockley diode pnpn structure. The CMOS parasitic pnpn structure can undergo regenerative feedback, leading to CMOS latchup. In SOI technology, the lack of the n-well region, p-well, and the physical isolation formed from the BOX prevents the coupling of these elements in the substrate wafer. As a result, the spatial separation between SOI n- and p-channel elements can be minimum without concern with CMOS latchup. In bulk CMOS technology, guard ring structures are used to minimize electrical overshoot, undershoot, and latchup (e.g., n-well guard rings and p+ substrate contacts). In ESD structures, the spacing of these guard ring elements must be separated to avoid interaction between the guard ring structures and ESD elements. As a result, the guard ring physical structure as well as the physical spacing relative to the ESD element can require a significant percentage of the allocated area for ESD design. As the ESD structure size is scaled or in small ESD networks, the percentage of area dedicated to the guard ring and the physical spacing may increase. In SOI technology, these can be eliminated. The elimination of the ESD guard ring structures has a significant impact on the total ESD area.

This area can also be taken advantage of by utilizing for active elements.

The lack of the vertical bipolar also simplifies the understanding of the SOI ESD diode element. In bulk CMOS, the ''ESD p+/n-well diode'' is a strong function of the physical design and the semiconductor process. From bulk CMOS ESD analysis, the semiconductor n-well process has significant effect on the ESD diode response. It was shown that the ESD robustness has a U-shape dependency as a function of the well sheet resistance. At high n-well sheet resistance, it has been shown by T. J. Maloney and S. Voldman that there exists a vertical bipolar current gain magnitude where the element responds as a vertical bipolar element. In SOI technology, the complexity of the response of the ESD SOI is significantly reduced because of the lack of the diode-bipolar duality, which exists in the bulk CMOS ESD element.

Another advantage of SOI ESD design is the lack of CMOS bulk floating gate tie-downs.

Floating gate tie-downs and well tie-downs can interact with adjacent CMOS devices. In SOI technology, the interaction does not occur because of the physical isolation introduced by the STI and BOX regions.

The physical separation of the n- and p-channel MOSFET from the bulk substrate allows the ability to bias or isolate the MOSFET body. This allows for symmetrical design practices as well as new opportunities for dynamic threshold MOSFET techniques to be used in circuit design. A second key issue is how this influences the response during ESD events. In bulk CMOS, charged device model (CDM) mechanism ESD failures occur in MOSFET gate structures in the MOSFET gate dielectric between the MOSFET channel region and the gate electrode. In ESD SOI technology, this mechanism does not occur; the disadvantage is that new mechanisms occur in new locations.

In SOI ESD design, there are still some underlying fundamental concepts that one can adhere to in order to have effective ESD results, similar to bulk silicon design:

_ Provide a solution that establishes a low-voltage trigger element, which can discharge a high current.

_ Provide spatially uniform current density within the trigger element.

_ Avoid non-uniform localized Joule heating within the trigger element.

_ Avoid electrical connections that exceed the breakdown voltage of the SOI MOSFET gate structure.

_ Operate the device under the SOI MOSFET second breakdown voltage.

_ Improve thermal stability of the SOI MOSFET structure.

The ability to provide a low-voltage trigger element can be achieved by the following techniques:

_ Minimum channel length MOSFETs to provide low SOI MOSFET snapback voltages.

_ Low threshold voltage SOI MOSFETs.

_ Gate coupling techniques.

_ Drain coupling techniques.

_ Body coupling.

_ Dynamic threshold SOI MOSFET coupling techniques.

SOI MOSFET ESD structures can discharge high currents given by the following means:

_ Low-resistance salicide films.

_ Low-resistance metallurgy (e.g., copper interconnects).

_ Low threshold SOI MOSFET for increased MOSFET current drive (e.g., maximize VG-VT).

_ Dynamic threshold voltage techniques.

Spatial uniformity is achieved in the MOSFET ESD structure by the following means:

_ Provide design symmetry in the metal and contact design.

_ Ballasting in the direction of the SOI MOSFET current flow.

_ Ballasting perpendicular to the direction of the SOI MOSFET current flow.

Avoidance of localized heating in the SOI MOSFET structure can be achieved by the following means:

_ Provide design symmetry in the metal and contact design.

_ Ballasting in the direction of current flow.

_ Ballasting perpendicular to the MOSFET current flow (e.g., lateral ballasting).

_ Introduce external ballasting elements in the SOI MOSFET ESD circuit.

_ MOSFET structures with extension implants or deep low-doped drain regions.

_ Increase body doping concentration to increase intrinsic temperature.

Avoidance of failure of the SOI MOSFET structure due to dielectric breakdown can be achieved via the following means:

_ Avoid SOI MOSFET gate-to-power rail direct connections.

_ Avoid MOSFET gate-to-pad direct connections.

_ Avoid SOI MOSFET gate-to-drain connections.

_ Avoid SOI MOSFET gate-to-source connections.

Avoidance of MOSFET second breakdown can be achieved by the following means:

_ Avoid the ESD MOSFET from undergoing MOSFET snapback.

_ SOI MOSFET gate-coupling techniques.

_ SOI MOSFET body- and gate-coupling techniques.

_ Increase doping concentration to raise the intrinsic temperature of the SOI MOSFET channel region.

Although many of the basic concepts of ESD design in SOI and bulk CMOS technology are similar, the actual physical layout of the structures and ESD network integration can be significantly different. Some of the fundamental distinctions are as follows:

_ No vertical parasitic devices exist.

_ No lateral device exists without formation of a MOSFET gate structure.

_ Vertical STI-bound p+ anode/n-well cathode diode structure does not exist in SOI technology.

_ n-well-to-substrate ESD diode elements do not exist in SOI technology.

_ Parasitic CMOS-based pnpn structures do not exist in SOI technology.

_ There are no vertical diode elements, hence no advantage to the area dependency.

_ There are no guard ring structures needed in SOI technology.

_ There are no local substrate contact guard rings for SOI devices.

As a result of the above issues, although the basic concepts in SOI design are the same, there are significant differences in the physical layout.

2. SOI ESD DESIGN: MOSFET WITH BODY CONTACT (T-SHAPED LAYOUT)

FIG. 1 H-shaped SOI MOSFET with SOI MOSFET body contact

MOSFET scaling on bulk silicon has been the primary focus of the semiconductor and microelectronic industry for achieving CMOS chip performance and density objectives.

Using SOI substrate wafers, many of the concerns and obstacles of bulk-silicon CMOS can be eliminated. CMOS-on-SOI provides low power consumption, low leakage current, low capacitance diode structures, good sub-threshold I-V characteristics, low soft error rate (SER), good SRAM access times, and other technology benefits.

One of the barriers of implementing SOI technology is the ''floating body'' issue. In the case of the floating body issue, where no MOSFET body contact exits, the MOSFET body potential will be a function of the capacitive coupling of the MOSFET. The MOSFET body potential will be capacitive coupled to the MOSFET drain, MOSFET source, and MOSFET gate electrodes. Current injected into the MOSFET body will also lead to charging effect. In the case of the ''floating body'' MOSFET, the SOI MOSFET threshold voltage will be modulated by the SOI MOSFET body and channel region. Additionally, the current and voltage history of the SOI MOSFET body will affect the voltage state of the SOI transistor.

To address the ''floating body'' condition of an SOI MOSFET, a MOSFET body contact can be placed to control the electric potential of the SOI MOSFET body. The SOI MOSFET body-contact adds an additional contact to the MOSFET structure (e.g., one additional contact beyond the bulk-MOSFET device). The concern of the SOI MOSFET body contact is twofold: first, the addition of the MOSFET body contact impacts chip area; and second, it impacts remapping of bulk-CMOS to SOI technology.

SOI MOSFET body-contact can be formed by defining a T-shaped region of silicon on the SOI BOX region (FIG. 1). The MOSFET source and drain are formed by using a dielectric and polysilicon gate structure. The SOI MOSFET polysilicon gate structure is contacted on one side that extends beyond the SOI MOSFET source and drain, where an electrical MOSFET gate contact is placed on the gate structure. On the opposite side, the SOI polysilicon MOSFET gate structure extends past the SOI MOSFET source and drain definition edge, but only partially to the end of the T-shaped silicon region to allow for the formation of the SOI MOSFET body contact. An SOI MOSFET body contact region is formed by a dopant implant in the silicon region, followed by an electrical contact. The region under the contact is doped with the same dopant polarity as the channel region, but of a higher doping concentration. The construction of the MOSFET gate, source, drain, and body forms an ''H-shaped'' structure (e.g., a T-shaped silicon region domain).

To provide ESD protection in SOI technology, one of the concerns was the lack of a vertical diode structure for electrical discharge. With the introduction of the MOSFET body contact, although it was a functional and layout design area and remapping concern, is an advantage for ESD protection. The introduction of the SOI MOSFET body allows for the ability to provide a lateral p-n diode structure.

FIG. 2 SOI double-diode ESD network using CMOS H-shaped (T-shaped) SOI MOSFETs with body contacts

FIG. 3 PMOS-defined SOI double-diode ESD network using T-shaped body-contacted SOI transistors

Using the T-shaped silicon domains, an SOI lateral diode structure can be formed. For example, using a p-channel SOI MOSFET device, the SOI MOSFET source and drain region can serve as the anode, and the SOI MOSFET n-type channel and body can serve as the cathode. Using an n-channel SOI MOSFET device, the SOI MOSFET source and drain region can serve as a diode cathode, and the SOI p-channel MOSFET can serve as the anode.

Because both the p- and n-channel SOI MOSFET bodies are disconnected from the well regions and the substrate, the electrodes can be changed and connected to input pads, power rails, or ground connections to form diode structures. In these cases, the SOI MOSFET gate structures are connected in fashion to avoid dielectric failure during ESD testing.

FIG. 2 shows an example of the SOI MOSFET design layout for a SOI double diode circuit that utilizes H-shaped (or T-shaped) SOI MOSFETs in a diode form. Using both a p- and a n-channel SOI MOSFET, a p-channel SOI MOSFET can serve as a ''SOI diode'' to the power supply rail, and the n-channel SOI MOSFET can serve as a ''SOI diode'' to the ground power rail. The SOI MOSET layout can be wired across both the SOI n- and p-channel MOSFETs electrically, connecting the MOSFET source and drain regions. The body and gate contacts can be electrically connected to the respective power supply rails.

An SOI ESD double-diode network can be formed using only SOI p-channel MOSFET body-contacted devices (FIG. 3). A PMOS implementation can use a SOI p-channel MOSFET source and drain as the anode of the SOI MOSFET to the power supply voltage, and a second SOI p-channel MOSFET whose SOI MOSFET body contact serves as the anode for the diode to the substrate power rail.

An SOI ESD double-diode network can be formed using only SOI n-channel MOSFET body-contacted devices (FIG. 4). An NMOS implementation can use an SOI n-channel MOSFET p-type body that serves as the anode to the power supply voltage, and a second SOI n-channel MOSFET whose SOI MOSFET source and drain serves as the cathode for the diode to the substrate power rail.

An ESD design considerations utilizing the T-shaped SOI MOSFETs with local body contacts are as follows:

_ A local SOI MOSFET body contact is needed to avoid lateral resistance effects along the SOI MOSFET channel.

_ The SOI MOSFET length should be of the order of the SOI MOSFET width for each unit.

These ESD design considerations limit the effectiveness to use these structures for large SOI ESD diode structures. It is also found that the ability to produce area-compact ESD designs with the T-shaped local body contact structures.

3. SOI ESD DESIGN: SOI LATERAL DIODE STRUCTURE

FIG. 4 NMOS-defined SOI double-diode ESD network using T-shaped body-contacted SOI

transistors

SOI lateral diodes for ESD protection can be constructed using a hybrid device that utilizes both the p-channel MOSFET and n-channel MOSFET without the use of body contact structure [10,11,13-16]. Using the p- and n-channel source/drain implants, a mask can be placed on the MOSFET gate structure where the p-channel MOSFET source/drain implant forms the anode, and the n-channel MOSFET source/drain forms the cathode. This can be formed in either n-or p-well regions. Source/drain features were defined using STI, which abuts the silicon dioxide (SiO2)BOX film. Dual work function silicided polysilicon gate electrodes were used for the MOSFET gate conductors. In a first implementation, a p-channel transistor used abrupt boron (B) source/drain junctions. The n-channel MOSFET source/drain has abrupt non-LDD arsenic junctions. MOSFET source/drain junction depths for both the n- and p-channel MOSFETs are 0.18 mm. ATiSi2 salicide film is formed on the source/drain junctions. The salicided polysilicon gate structure is placed on a 7.7-nm SiO2 gate dielectric. In the SOI lateral diode structure, the polysilicon length was set at 1.2 mm.

The mask to define the p+ and n+ implants must be placed over the polysilicon-gate structure. In this fashion, the polysilicon-bound diode structure has a polysilicon film with two different dopant types and work functions along the device channel length. With the placement of this structure on a BOX, the trench isolation abuts the BOX film, isolating the polysilicon-bound diode structure from adjacent structures. In a 0.25-mm technology, the lateral polysilicon-bound diode structure was studied as a function of the SOI diode perimeter and the polysilicon MOSFET gate structure channel length.

FIG. 5 Cross-section of an SOI lateral gated diode structure

3.1 SOI Lateral Diode Design

FIG. 5 shows a cross-section of the SOI lateral diode structure. FIG. 6 shows the SOI polysilicon diode ESD layout design. In the design layout, the anode region is enclosed by a polysilicon gate structure. Since the design is an enclosed gate structure, it is necessary to provide an electrical contact to the lateral SOI gate structure. The electrical contact to the gate must be made over the isolation structure [13-16].

3.2 SOI Lateral Diode Perimeter Design

FIG. 7 shows the ESD robustness of a polysilicon-bound gated diode structure as a function of polysilicon perimeter. HBM results show that the ESD results improve linearly with increasing diode perimeter with a design Lpoly of 1.2 mm. In this structure, the structure size was increased using multiple diode fingers. With no substrate coupling, as the number of fingers increases, the ESD results also increase with the diode perimeter.

FIG. 6 SOI lateral diode layout design highlighting the polysilicon gate connection Figure 6.7

FIG. 7 ESD results of a ESD polysilicon gated diode structure as a function of polysilicon gate perimeter (Lpoly = 1.2 mm)

3.3 SOI Lateral Diode Channel Length Design

The SOI lateral diode design demonstrated a weak sensitivity on the SOI lateral diode channel length. FIG. 8 shows the HBM ESD results as a function of polysilicon length for an 800-mm perimeter diode structure. Experimental results demonstrated a large window for channel length operability. In this structure, as the channel length decreases, the p+ and n+ diffusion regions approach each other. At some physical distance, the ESD results decrease. Additionally, as the length of the structure increases, ESD results decrease.

3.4 SOI Lateral p+/n-/n+ Diode Structure

This structure can be built in either an n-well structure or in a p-well structure. In the case of an n-well structure, the SOI lateral polysilicon-bound diode is a p+/n-/n+ implementation.

FIG. 9 shows the cross-section for the SOI p+/n-/n+ diode structure. In this structure, the n-type halo and p-type halo implants are in the n-well region. The metallurgical junction is formed at the n-well to p-channel MOSFET source/drain region.

FIG. 8 SOI lateral diode design ESD results as a function of channel length

FIG. 9 SOI ESD lateral diode: p+/n-/n+ structure

3.5 SOI Lateral p+/p-/n+ Diode Structure

FIG. 10 shows the cross-section for the SOI p+/p-/n+ lateral diode structure. In this structure, the structure is formed in a p-well. In this structure, the n-type halo and p-type halo implant are in the p-well region. The metallurgical junction is formed at the p-well to n channel MOSFET source/drain region.

3.6 SOI Lateral p+/p-/n-/n+ Diode Structure

In the prior implementations, either a p-well or an n-well was utilized for the SOI lateral diode structure. Using the n- and p-channel MOSFET source/drain junctions, as well as both p- and n-well, a SOI lateral p+/p-/n-/n+ diode structure can be formed. FIG. 11 shows the cross-section for the SOI p+/p-/n-/n+ diode structure. In this structure, the n-type halo and p-type halo implants are in the p-well region. The metallurgical junction is formed at the p-well to n-well intersection. In this structure, one advantage is that a non-abrupt junction is formed at the metallurgical junction. The structure was first implemented by M. D. Ker and H. Tang and demonstrated superior results compared to the single well lateral SOI structure.

FIG. 10 SOI ESD lateral diode: p+/p-/n+ structure

FIG. 11 SOI ESD lateral diode: p+/p-/n-/n+ structure

3.7 Un-gated SOI Lateral p+/p-/n-/ n+ Diode Structure

SOI ESD structures, whether using SOI MOSFETs lateral diode structures or even buried resistor (BR) elements, all contain MOSFET gate structures. One of the key ESD design concerns is the additional loading capacitance of the MOSFET gate structure and its dielectric integrity. An SOI lateral device can be constructed by the removal of the MOSFET gate structure. FIG. 12 shows the p+/p-/n-/n+ structure without the MOSFET gate structure, first implemented by M. D. Ker and H. Tang [17-19]. The advantage of this implementation is excellent ESD results; the disadvantage is the additional semiconductor processing to remove the SOI MOSFET gate structure.

3.8 SOI Lateral Diode Structures and SOI MOSFET Halos

In the design of SOI ESD lateral p-n gated diode structures with a single well region, a n type halo is formed near the p-channel MOSFET source/drain region, and a p-type halo is formed near the n-channel MOSFET source/drain region. With the use of a single well dopant type under the gate structure, one of the two halos is the opposite dopant polarity of the well structure. In this case, a ''bad halo'' is present that adds additional resistance to the SOI diode structure; this was first observed by N. Zamdner. To provide a good SOI ESD protection structure, the ''bad halo'' is masked to prevent placement in the channel region.

FIG. 12 SOI un-gated lateral diode structure

FIG. 13 An SOI buried resistor (BR) structure utilizing a separate implant and a MOSFET of the same dopant polarity

4. SOI ESD DESIGN: BURIED RESISTORS (BR) ELEMENTS

In SOI circuit design, a high tolerance resistance element is desired for circuit design point accuracy and circuit matching. SOI resistor passive elements are also needed for analog applications and ESD design. The SOI buried resistor (BR), as used in CMOS technology, can be implemented into SOI technology using either an additional silicide block mask or the SOI MOSFET gate structure as the silicide block mask (FIG. 13). The structure is formed by either implanting through the SOI MOSFET polysilicon gate structure, or placing an implant in an isolation region and placing a MOSFET of the same dopant type over the implanted region. In this fashion, the electrical contacts of the BR input and output are formed by the MOSFET source and drain region. The BR implant is typically a lower doped implant below the doping concentration of the SOI MOSFET source and drain.

This element is of significant interest for ESD design and its methodologies. BR elements can be used as ballasting elements, diodes, and lateral npn devices for ESD design applications. As in bulk CMOS, BR resistors can be used as ballasting elements for off-chip driver (OCD) networks and receiver networks. For SOI technology, there are a few key distinctions in the ESD response of the SOI BR element compared to the bulk BR element:

_ SOI BR elements have higher thermal resistance to the substrate leading to a different thermal response during ESD events, and hence will have a different thermal response.

_ SOI BR elements do not form a diode structure with the substrate; this prevents current flow in negative polarity ESD events leading to different ESD failure mechanisms and responses.

_ SOI BR elements are isolated from the bulk and do not form a metallurgical junction with the substrate; CDM current flow from the substrate to the BR dopant region does not occur.

_ SOI BR elements must remove halo implants to avoid higher series resistance during both functional and ESD events.

On the first issue, because of the BOX region, the self-heating will be of a higher magnitude in the SOI BR element compared to the bulk CMOS BR element. This will lead to a different functional as well as thermal response.

SOI BR elements do not form a diode structure with the substrate; this prevents current flow in negative polarity ESD events, leading to different ESD failure mechanisms and responses. During negative HBM and MM events, the ability to discharge current from the input pad to the substrate is typically achievable using bulk BR elements; in SOI, the SOI BR element cannot discharge the negative polarity event to the substrate, leading to a failure mechanism within the BR, or the need for an alternative ESD solution. Consequently, SOI BR elements are isolated from the bulk and do not form a metallurgical junction with the substrate; this leads to the lack of interaction during CDM events from the substrate. As a result, the CDM current will find an alternative current path.

SOI BR elements are formed by placing an n-channel MOSFET into an n-well or alternative n-implant; this leads to a series p-type halo implant in the resistor structure, and a higher series resistance during both functional and ESD events.

5. SOI ESD DESIGN: SOI DYNAMIC THRESHOLD MOSFET (DTMOS)

SOI dynamic threshold MOSFET (DTMOS) has the advantage of low trigger voltages, high current drive, and high Ion/Ioff current ratio [23]; SOI DTMOS devices have natural advantages for ESD protection. S. Voldman first demonstrated the use of DTMOS networks for ESD protection in 0.22-mm SOI technology. For the optimization of the SOI DTMOS structure, three basic designs were used. Three different structures were constructed where in all cases a polysilicon ring was formed about the n+ drain, and the polysilicon MOSFET gate structure enclosed the body contact and the n+ drain (FIG. 14).

FIG. 14 Dynamic threshold MOSFET device

FIG. 15 Transmission line pulse (TLP+ I-V characteristic of a SOI off-chip driver (OCD) only, and the I/O OCD with three different SOI DTMOS ESD elements (10 finger structures)

The n+ MOSFET source enclosed the polysilicon ring MOSFET gate structure. In all these structures, the p+ body contact (at the drain side) abuts the polysilicon MOSFET ring that serves as a body contact for the MOSFET and forms a lateral SOI gated p-n diode structure (SOI Lubistor) adjacent to the MOSFET structure. In the first design, the p+ body contact abuts the n+ drain. In this implementation, it was believed that the butted structure would provide the lowest dynamic resistance, and is the most space efficient. The butted structure also is bridged by cobalt salicide. In the second design of the DTMOS device, the p+ body contact is separated from the n+ drain region. This design will avoid any technology-related concerns of butted structures and allows for STI of the body-contacted region from the MOSFET drain region. In the third structure, the p+ body contact is separated by a polysilicon gate structure from the n+ drain. The third implementation provides polysilicon isolation of the body and the MOSFET drain region, avoiding any STI pull-down mechanisms, independent biasing capability, and introduces an additional lateral diode between the body and the source.

Our first point of interest was to determine which structure provided the lowest RON, and avoided any reliability issues. FIG. 15 shows transmission line pulse (TLP) results of an SOI OCD network and the three different large dynamic threshold body- and gate-coupled ESD diode networks.

FIG. 16 TLP I-V characteristic of a SOI DTMOS element for various body contact width-to DTMOS device width

In FIG. 15, a cascaded SOI driver with the first transition of the first MOSFET triggering at 4 V is followed by the second MOSFET triggering at 8.4-V SOI MOSFET. In the measurements, the body- and gate-coupled DTMOS ESD device is configured with the drain, gate, and body connected to the input node and the source connected to VDD power supply. The results show that the SOI body- and gate-coupled DTMOS ESD network with STI between the p+ and n+ region provide a higher RON relative to the other two designs (e.g., RON _ 4 _). This can be understood in that the STI does not provide any means of conduction and causes more current crowding and resistance. In the second implementation, where the polysilicon gate region is used between the body and the drain, the addition of the extra diode region provided a lower lateral body resistance providing a lower RON in the ESD network (RON _ 2.8 _). In the third implementation, where the p+ body and n+ drain are abutted, the RON _ 1.2 _. In this structure, the lowest voltage is established at the I/O OCD because of the steep on-resistance. In conclusion, this study showed that the most suitable and efficient structure for a dynamic threshold SOI ESD structure is the structure where the p+ and n+ implants are abutting.

To better understand the operation of these structures, it is important to evaluate a matrix where the ratio of the MOSFET drain width and the body width are varied while the total length of the structure remains fixed. In our experimental matrix, as the body width was increased, the MOSFET width was decreased so that the total perimeter of the source is the same width.

FIG. 16 shows an example of the body- and gate-coupled DTMOS ESD network, where the ratio of the body and drain width are varied. Defining the body contact width, WBC, and the drain width WN we can form a ratio or percent body-contact as WBC /(WBC ) WN). In FIG. 16, TLP I-V measurements are taken for devices as a function of the percentage of body contact (e.g., for the cases of 13%, 27%, 40%, and 53% body contact).

With the observation of the 13% body contact, the first TLP I-V characteristic shows that it follows a monotonically increasing current from 0 to 4 V, and this is followed by snapback of the DTMOS device. As the body voltage rises, the diode formed between the body contact and the MOSFET source first turns on, and at the same time, the MOSFET threshold voltage decreases. As the gate voltage exceeds the threshold voltage, the dynamic threshold MOSFET device also turns on, with a high Idsat. When the voltage across the structure approaches the snapback voltage, this structure undergoes a snapback state. As the percent body contact ratio increases, the dynamic on-resistance also increases. With lower on resistance, the discharge current capability improves.

6. SOI ESD DESIGN: DUAL-GATE (DG) MOSFETs

With the continued struggle to scale MOSFET devices to the Sub-tenth Micron Era, semiconductor engineers have been pursuing new directions in MOSFETs. To achieve both high density and high performance, the MOSFET is leaving the paradigm of the MOSFET evolution in two-dimensions and must address a new revolutionary move to the third dimension. A potential evolutionary path for the MOSFET was a two-dimensional (2-D) bulk CMOS planar MOSFET device, to the 2-D single-gate (SG) SOI MOSFET, to the 2-D dual-gate (DG) SOI MOSFET device. SOI ESD circuit implementations in SG-SOI devices can be extended into DG-SOI.

The DG-SOI MOSFET was to provide a means to produce more current for a given planar device. In the case of a DG-SOI MOSFET structure, a second gate is formed either within the BOX region or below the BOX region. The problem with the DG-SOI MOSFET is processing costs and alignment of the second gate. The formation of the second gate structure within the BOX region will require either growth over the first gate, or bonding and etch-back style process integration. A second gate can be formed under the first gate structure using an implanted gate structure, but this suffers density, loading capacitance, leakage issues, and too thick of a gate oxide for the second gate structure. As a result, the progress in the area of a buried second gate has had little success of implementation.

7. SOI ESD DESIGN: FINFET STRUCTURE

Because of the progress in the DG-SOI MOSFETs, new directions have been taken to move in ''surround'' gate or ''wrap-around'' gate structures. In 1986, Takahashi et al. proposed the Surround Gate Transistor (SGT) device with the objective of achieving a smaller transistor structure. D. Hisamoto et al. proposed the Fully Depleted Lean Channel Transistor (DELTA) device, which was a novel vertical ultra-thin SOI MOSFET structure. This evolution has progressed toward a silicon pillar device with a wrap-around gate in both bulk CMOS and in SOI technology. Tang et al. developed a quasi-planar double-gate device known as a ''FinFET.'' Concepts of surround gates, wrap-around gates, and non-planar dual gates were all different strategies on constructing the non-planar MOSFET into narrow width silicon pillars, leaving the wafer surface to form the 3-D MOSFET structures.

In a FinFET structure, the key design parameters is the fin height H, fin thickness, Tsi, and the effective channel length, Leff, and the number of parallel fin structures, NFin. For analysis of the FinFET, we can define an effective channel length as...

In a double-gated (DG) FinFET device, the contours merge, at…

and we can define an effective film thickness as….

A more accurate solution derived the following relationship […]

The SOI FinFET structure forms a parallel-piped surrounded by isolation material below and above the conducting region, and the thermal sinks formed by the boundary conditions.

For evaluation of a parallel-piped in an infinite insulating medium, let us assume a source has the dimension of a SOI FinFET width W=Teff in the x-dimension, and Leff in the y dimension, and FinFET height H in the z-dimension, but applying a parallel-piped displaced distance D below the boundary condition z=0 and an image source of equal and opposite strength above the z=0 plane at z=D

From this solution, assuming the FinFET is surrounded by insulating regions, the solution for self-heating within the SOI FinFET can be obtained. For electrostatic discharge (ESD) phenomena, there are two issues. The first issue is how the current distributes between multiple parallel FinFET devices. A second issue is the relative width of a current constriction to the effective fin width and height. The first issue is similar to any other parallel configuration in that the current distribution is a function of the ballasting and matching between any two parallel elements during second breakdown. The second issue is the volumetric nature of the current constriction and relative scale length compared to the dimension fin height H and fin width Teff.

From our earlier analysis of current constriction in planar MOSFETs, we can anticipate that the relationship may have a one-to-one equivalency of planar MOSFET width to the fin height, of N parallel FinFETs, assuming that there is conduction in some number M where M is equal to or less than N.

When the fin height and width are of the same order of magnitude, it is possible that the arithmetic mean may serve as a better metric, where the Heff and the Teff are the ESD effective widths based on the percentage of the fin height and the electrical effective FinFET width.

8. SOI ESD DESIGN: STRUCTURES IN THE BULK SUBSTRATE

In ultra-thin film SOI (UT-SOI), fully depleted SOI (FD-SOI), and highly scaled partially depleted SOI (PD-SOI), the ability to provide ESD protection will be more difficult.

Additionally, in mixed signal application, where some circuits are on SOI and others are in the bulk, there is the possibility of producing ESD structures in the bulk substrate. M. Chan and C. Hu demonstrated a reduction in the ESD robustness of MOSFET structures formed on SOI wafers, and proposed a hybrid process where some circuits are formed on the SOI and other are formed in bulk CMOS wafer; this is achieved by removal of the SOI BOX region on some sections of the substrate wafer. A disadvantage of this method is the topography issues and cost. Alternative methods were proposed forming dual SOI films vertical ESD SOI structures with uniform topography above the BOX, and three dimensional (3-D) SOI ESD structures and contact structures below the buried oxide.

The dual SOI film will lessen the impact of scaling and allow vertical SOI structures, and the 3-D SOI ESD under the BOX will allow for vertical integration, uniform topography, reduce chip area, and allow utilization of the SOI bulk region.

9. SOI ESD DESIGN: SOI-TO-BULK CONTACT STRUCTURES

In SOI wafer, the substrate region, the BOX, and the thin silicon film and corresponding interconnects form a capacitor-like structure, where the BOX serves as an insulator. In the case of no electrical connection between the front and back of the wafer, the electrostatic potential of the substrate wafer will modulate the SOI electrical circuitry. S. Geissler showed that by charging or discharging the substrate wafer, the logic state of the functional circuits could be modified during functional testing; it was shown that by handling the wafer back side, the logic state of SOI microprocessors could be altered. Additionally, failure of the BOX region can be observed from CDM-like ESD events in the case of no electrical connection. Without a means to provide the ability to shunt the electrical charge between the front and the back of the wafer, it is anticipated that electrical discharge will occur along the edge of a SOI semiconductor chip (e.g., surface discharge) or failure of the BOX. To address both the functional and this ESD issue, electrical contact structure can be formed by etching through the BOX to establish a contact structure. SOI contact structure consists of metal or polysilicon contact structures. These contacts serve two roles: a first role is an electrical contact to bias the backside and prevent electrical discharge, and a second role for the formation of ESD structures under the BOX.

10. SUMMARY AND CLOSING COMMENTS

In Section 5, an introduction of SOI ESD device structures highlighted the use of a MOSFET and lateral SOI diode structures, which have been used to allow the integration of SOI into a mainstream applications, such as microprocessors. The focus of this Section was on SOI lateral-gated diode structures, since these are the primary vehicle of ESD protection today in partially depleted SOI, ultra-thin SOI, and radio frequency SOI (RF-SOI). DTMOS SOI was also discussed; these elements were utilized as prototypes for future applications.

Extension of these concepts can be utilized for dual gate SOI (DG-SOI) and 3-D SOI structures.

In Section 6, the design and layout of off-chip driver (OCD) networks is discussed, where OCD design and layout for single-MOSFETs and stacked (e.g., series cascode) MOSFETs is discussed. Section 6 will discuss the issue of separated versus integrated series cascode MOSFET design. The understanding of design and layout of OCD networks is important for achieving good ESD results in bulk CMOS, triple well CMOS, and BiCMOS Silicon Germanium applications.

PROBLEMS

1. Given an SOI double-diode network on an input node. Assume that the gate of the SOI p+/n+ element is connected to its cathode. Assume the top element is connected to a VDD power supply, and the second element is electrically connected to VSS power supply. Assume an oxide breakdown voltage of VOX, derive a relationship for the maximum pad voltage when gate oxide breakdown occurs. Evaluate all positive and negative polarity cases.

2. For the network in Problem 1, assume that the circuit is used to interface with a second power supply voltage VDD2, which exceeds VDD. Derive the voltage conditions across the gate oxide of the ESD network. Derive the condition for breakdown to occur for all positive and negative states where the input can be varied from VDD2 to ground potential.

3. To avoid electrical failure of SOI ESD networks, the gate electrode can be de-coupled from the SOI diode cathode region. This can be electrically connected to an inverter circuit whose input is zero, and whose output is the power supply voltage VDD.

Assuming a long channel inverter network with a p-channel resistance and n-channel resistance, derive the voltage across the gate electrode for the mixed voltage states (e.g., VDD2 and VSS) on the input pad. Derive when failure will occur in the oxide.

4. For resistor ballasting, an SOI MOSFET is to be used as a ballasting resistor. How can you design an SOI MOSFET in order to use the body and channel as a ballast resistor? How can you integrate the SOI MOSFET ballast resistor with an SOI MOSFET for a OCD network?

5. An SOI MOSFET is used to form a resistor using two-body contacts and the channel region. Derive an equation for the SOI body resistor element. Assume we desire the resistor to be a pinch resistor by biasing of the SOI MOSFET source and drain junctions. Derive a model for the resistor based on a source and drain voltage condition.

6. For an SOI network, an SOI half-pass transmission gate is used in an SOI MOSFET receiver network. Assume a semiconductor chip is charged through the substrate.

Assume the substrate region under the BOX is electrically connected to the VSS power rail. Assuming that during an CDM event, the charge does not flow through the SOI MOSFET receiver network, but instead transfers from the VSS to the VDD power rail through the chip capacitance. The charge is transferred from the VDD power supply to the input pad through the SOI half-pass transmission gate through the gate structure.

Derive the voltage conditions across the half-pass transistor when the signal pad is grounded. How do you provide an ESD design solution to avoid SOI half-pass transistor failure?

7. SOI ESD networks can be placed under the BOX region. Estimate the capacitance loading of an ESD device under the BOX region for a minimum design rules, and compare this to an equivalent element above the BOX region.

8. SOI lateral p-n ESD devices can be constructed using the polysilicon gate electrode as the block mask between the p+ region and the n+ region. Using a mask, the gate region can be removed. Compare the capacitance loading effect of a gated and ungated SOI lateral p-n diode. Assume the region between is the same implant type.

9. Using Green's function analysis, derive a model for the SOI BR element, assuming the resistor element is a parallel-piped region.

10. Derive a thermal model for the BOX using a thermal resistor and thermal capacitor.

Derive the change in the temperature as a function of BOX scaling.

11. Given an SOI FinFET structure, how many parallel FinFETs are needed to discharge a 1 kV HBM pulse? Assume the SOI FinFET conduction is the full width of the structure and evenly ballasted through all parallel elements.

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