Plug-in data acquisition boards: Counter/timer I/O boards

Counter/timer circuitry is useful for many applications, including digital event counting, digital pulse timing, one shot and continuous clocked outputs and generating waveforms with complex duty cycles.

All of these applications can be implemented using a simple counter, which comprises a source input and gate input, a single output and an internal n-bit count register, as shown in ill. F.35.

ill. F.35 Simplified model of a counter

A counter is a digital device that responds to and outputs TTL compatible signals, counting input signal transitions at its source input by incrementing its internal count register every time a transition occurs. The source input therefore provides the time-base for the operation of the counter. The counter can be configured to count either negative going (high-to-low) transitions, or positive going (low-to-high) transitions, of signals occurring at the source input. The internal count register can be read by software at any time.

The gate input can be used to enable/disable the function of the counter, by enabling or disabling counting dependent on the current signal level at the gate input. In this mode, the active level of the gate input can be configured to enable counting when the gate input is at a high level and disable counting when it's at a low level, or vice-versa. The counter may also be configured to begin counting input transitions only after a transition of the signal at the gate input, that is, the gate acts as a count trigger. In this mode, the active edge of the gate input signal can be configured to allow counting only after a rising-edge (low-to-high) transition of the gate input, or alternatively, a falling-edge (high-to-low) transition of the gate input. In all modes, counting begins at the next active clock edge after the active gate signal.

When the counter is used with no gating, software initiates the counting sequence.

The output signal can be configured, depending on the mode of operation of the counter, to either toggle states or pulse, when the count register reaches its terminal count (TC). If the signal output from another counter is used as the gate input, thereby enabling and disabling the count as required, complex waveforms with specified duty cycles and frequency could be generated. This is dependent on the mode of operation of the counter, since in some modes the gate input has no effect.

ill. F.36 shows the general operation of a counter configured for high-level gating and positive-edge triggered gating. The output signal is configured for positive polarity and is shown for both pulse-output and toggle mode on reaching terminal count (TC). For simplicity, the counter is operating in count-up mode and the count is set to five (5).

ill. F.36 Waveforms showing general operation of a counter

Two commonly used counter/timer chips are available which provide counters with the signal functions described above. The 8254 counter/timer chip contains three independently programmable 16-bit counters. it's regularly used on plug-in A/D boards as a pacer clock and pulse trigger for accurate timing of A/D sampling rates and D/A conversion rates. it's often included on multi-purpose DAQ boards as an uncommitted counter/timer to perform any necessary counting or timing functions required of an application. A more frequently used counter/timer chip for dedicated timer/counter I/O boards is the AM9513 chip, a powerful and flexible device, consisting of five independent 16-bit counters. A typical counter/ timer I/O board employing the AM9513 chip is shown in ill. F.37.

ill. F.37 Typical counter/timer I/O board

As details of the AM9513 operation are quite complex they will not be detailed here, however, the most important specifications of a counter/timer chip are its resolution, which is simply the bit width of the internal count registers, and clock frequency. A counter/timer chip with 16-bit resolution means that each of its counters can count up to 65,535. A higher resolution simply means that each of the counters can count higher. Greater count resolution can be achieved by connecting the output of one counter to the source input of another counter. When two or more counters are cascaded together, extremely large counts can be performed. e.g., two 16-bit counters, when cascaded to make a 32-bit counter, can count to over four billion.

The clock input to a counter is a physical connection to a high frequency stable clock source, which is usually internally-divided to more suitable clocking frequencies. The frequency of the clock source becomes important since new counts are loaded and the internal counter is decremented on a transition of the clock pulse, usually on the falling edge of the clock. Consider a signal applied to the source input that has a higher frequency than the clock source. The input signal may perform several transitions before the next clocking edge allows the internal counter to be decremented, leading to inaccurate measurement of the source input signal. Therefore, the higher the clock frequency, the faster the internal count register can be decremented and the higher the frequency signals on the source input, which can be detected and accurately measured. In addition, the higher the frequency of the clock source, the higher the frequency of pulses, square waves and complex waveforms, which can be generated on the output.

Counter/timers can be configured to operate in many different modes of operation, the number of modes, and the functions performed in each mode dependent on the manufacturer of the counter/timer chip. Several of the most common functions that can be performed by counter/timers are demonstrated below.

Generating waveforms:

Generating waveforms of variable duty cycles is straightforward. Consider a counter on the 8254 counter/timer chip, configured for mode 1 operation, in which the count is triggered by the active edge of the signal on the source input. The next clock pulse after this count-trigger, the internal counter is loaded with the initial count ( N), the output goes low, and the count begins. The output will remain low for N clock pulses before returning high and remaining high until the next clock pulse after the next active edge of the source input signal.

By using this method, output waveforms of specified duty cycle and frequency can be generated. The frequency of the waveform is exactly the same as the frequency of the signal applied at the source input. The duty cycle is determined by dividing the period T1 for which the output signal remains high, divided by the period of the output signal T3= T1 + T2.

When a waveform is generated in this way there will be an uncertainty in the period of the output waveform compared to the period of the signal on the source input, of up to one clock period. This error depends on when the count trigger occurs in relation to the active edge of the clock signal.

Measuring pulse width:

Counters can be used to measure the width of a pulse by applying the unknown pulse signal to the gate input of the counter and counting the number of cycles of a known frequency clock signal applied to the source input. The known clock signal can be derived from the clock input of the counter/timer chip, an external clock source, or from the output of another counter configured to produce a periodic waveform of the required frequency.

When a counter is configured to enable counting on the active high level of the gate input, the internal counter starts counting the source input transitions at the next active transition, after the gate input pulse goes high and stops counting at the end of the pulse. The duration of the gate input pulse ( Tpw) is found by reading the count register contents, determining the number of known clock transitions that occurred ( N), and multiplying this by the time between each active transition of the clock ( TS). In this case, it does not matter whether the count occurs on the positive or negative going edge of the source input. What is more important is the frequency of the known clock signal applied to the source input. As shown in ill. F.38, an error can occur in the counting of the clock transitions, depending on when the pulse begins and ends in relation to the active edge of the clock input. This error can be almost two full clock cycles. Clearly, the higher the frequency of the clock signal, the smaller the counting error will be, and the higher the resolution of the pulse measurement. Care must also be taken not to choose too high a frequency clocking source input as the counter may reach its terminal count before the end of the pulse.

ill. F.38 Measuring an unknown pulse width

Consider a 500 kHz clock signal, with a clock period of 2 µs, applied to the source input.

As a 16-bit counter can count up to 2 16 -1 = 65,535 transitions of the clock input, the maximum measurable pulse width will be 65,535 * 2 µs = 131 ms. Decreasing the frequency of the clock input source increases the pulse width that can be measured.

Selection of the frequency of the clocking source input is therefore a compromise between the resolution and accuracy required of the measurement and the pulse width that must be measured.

Measuring an unknown frequency:

Counters can also be used to measure the frequency of a periodic square wave, irrespective of its duty cycle. This is accomplished by applying the unknown signal to the source input of the counter and counting the number of cycles of the signal during a fixed duration pulse applied to the gate input. The fixed duration gate input signal can come from an external source or from the output of another counter, configured to produce a pulse of the required duration.

As was the case for pulse width measurement, the counter is configured to enable counting on the active high level of the gate input. The internal counter starts counting the source input transitions at the next active transition after the gate input pulse goes high and stops counting at the end of the pulse. The frequency of the signal at the source input, ( fS), is found by determining the number of signal transitions ( N), which occurred and dividing this by the period of the fixed duration gate input pulse, Tpw. fS = N / Tpw. This is shown in ill. F.39.

ill. F.39 Measuring an unknown frequency

The lower the frequency of the signal that must be measured, the greater should be the fixed duration pulse width to achieve the same resolution and accuracy. If however, the duration of the fixed pulse, ( Tpw), is too long compared to the clock period, ( TS), of the unknown frequency signal being measured, the counter may reach its terminal count before the end of the pulse. Therefore, the selection of the duration of the fixed pulse at the gate input is a compromise between the resolution and accuracy required and the frequency of the input signal being measured.

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