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AMAZON multi-meters discounts AMAZON oscilloscope discounts This section focuses on the PLC hardware fundamentals and logic programming for the Siemens S7-1200. Concepts covered are applicable to other types of PLCs. [Note: Figures and Tables to be added soon!] GOALS:
A programmable logic controller (PLC) is a microprocessor-based computer unit that can perform control functions of many types and varying levels of complexity. PLC programming is a major task because in addition to requiring knowledge of the specific ladder-logic development environment and associated utilities, it assumes familiarity with the control application domain. Understanding of the PLC hardware details, human-machine interfaces (HMIs), and communication fundamentals is a must. This section focuses on the PLC hardware fundamentals and logic programming for the Siemens S7-1200. HMIs and communication will be addressed in Section 5 === Fig. 1 Typical S7-1200 processor. Memory card slot CPU LEDs PROFINET connector I/O LEDs 1 4 Wiring connector 5 2 3 === 1 PLC Hardware The S7-1200 PLC provides the flexibility and power to control a wide variety of devices in support of automation needs. The compact design, flexible configuration, and powerful instruction set combine to make the S7-1200 a perfect solution for controlling a wide variety of applications. The central processing unit (CPU) combines a microprocessor, an integrated power supply, input circuits, and output circuits in a compact housing to create a powerful PLC. After you download your program, the CPU contains the logic required to monitor and control the devices in your application. AMAZON multi-meters discounts AMAZON oscilloscope discounts The CPU monitors the inputs and changes the outputs according to the logic of your user program, which can include Boolean logic, counting, timing, complex math operations, and communications with other intelligent devices. 1.1 S7-1200 Processor The CPU provides a PROFINET port for communication over a PROFINET net work. PROFINET uses the Ethernet network protocol as in offices and information technology (IT) departments. However, its capabilities have been enhanced to meet the far-tougher conditions encountered in factory automation, process automation, and other industrial applications. More coverage of communication, net working, and PROFINET is provided in Section 5. Communication modules are available for communicating over RS485 and RS232 networks. Fig. 1 shows a typical Siemens S7-1200 processor. The SIMATIC S7-1200 system comes in three different models: CPU 1211C, CPU 1212C, and CPU 1214C. The following five areas are pointed out: 1. Status light-emitting diodes (LEDs) for the onboard input-output (I/O) 2. Status LEDs for the operational state of the CPU 3. PROFINET connector 4. Memory card slot (under door) 5. Removable user wiring connector 1.2 Operating Modes of the CPU The CPU has three modes of operation: STARTUP, STOP, and RUN. The following are the characteristic of each of the three CPU modes: • In STOP mode, the CPU is not executing the program. Projects cannot be executed in this mode. • In STARTUP mode, the startup organizational blocks (OBs) are called by the operating system. OBs (if present) are executed once and usually contain setup instructions. Interrupt events are not processed during the startup phase. • In RUN mode, the scan cycle is executed repeatedly in the processor memory, and outputs are activated according to the implemented program logics. The program cannot be downloaded in this mode. === Fig. 2 Communication module. Status LEDs 1 Communication connector 2 === 1.3 Communication Modules The S7-1200 family provides communication modules (CMs) that provide critical additional functionality to the system. There are two communication modules: RS232 and RS485. The CPU supports up to three CMs. Each CM connects to the left side of the CPU (or to the left side of another CM that is connected to the CPU). Fig. 2 shows a typical Siemens S7-1200 communication module. The following areas are pointed out: 1. Status LEDs for the communication module Communication connector === Wiring connector Status LEDs 1 2 Fig. 3 Signal board. === 1.4 Signal Boards A signal board (SB) allows user to add I/O module to the CPU. One SB can be added inside the front of any CPU to easily expand the digital or analog I/O with out affecting the physical size of the controller. SBs can be connected to the right side of the CPU to further expand the digital or analog I/O capacity. CPU 1212C accepts two and CPU 1214C accepts eight SBs. Fig. 3 shows an S7-1200 signal board. The following are the two available SB types: • SB with four digital I/O (2 × dc inputs and 2 × dc outputs) • SB with one analog output 2.1.5 Input-Output Modules I/O modules are of three types: digital, analog, and special. Digital I/O modules provide discrete ON/OFF voltage-type signals, and analog I/O modules provide variable (minimum to maximum value) voltage or current signals. An example of a special module is a high-speed pulse (HSP) counter or an ASCII module. Digital Input Modules As shown in Fig. 4, an input module performs four main tasks: it senses the presence of an input signal, maps the input signal (which is typically a 120 Vac or 24 Vdc to a low dc voltage), isolates the input signal from the mapped output signal, and outputs a direct-current (dc) signal to be sensed by the PLC processor (CPU) during the input scan cycle. Digital Output Modules An output module operates in the opposite manner as an input module. It acts as a triode for alternating current (TRIAC) switch connecting any selected input to the module's alternating-current (ac) or dc voltage, as shown in Fig. 5. The output module having the matched terminal address receives an output command from the CPU. The output module performs the voltage switching to the selected terminal output point. TRIAC is a trade name for an electronic component that can conduct current in either direction when it is triggered (turned ON) and is formally called a bidirectional triode thyristor or bilateral triode. The bidirectional property makes TRIACs very convenient switches for ac circuits, also allowing them to control very large power flows. Fig. 4 Digital input module. Fig. 5 Digital output module. 1.6 Power Supply The main function of the power supply is to convert the 120/220-Vac input to the 24 Vdc required for the PLC operation. The power supply has three main components: line conditioner, rectifier, and voltage regulator. The line conditioner purifies the input ac voltage waveform to a smoothed sine wave. The rectifier converts the stepped-down input ac voltage to the required dc voltage level, as shown in Fig. 6. The voltage regulator maintains a constant dc output voltage level by filtering and reducing existing ripples. 1.7 S7-1200 PLC Memory Organization/Specifications The S7-1200 PLC is designed to be a microcontroller with compact size, limited resources, and excellent capabilities. Tbl. 1 shows the specification and capabilities of the S7-1200. 1.8 Processor Memory Map and Program Organization This section briefly introduces the structure of the Siemens S7-1200 processor memory. It also covers the concept of structured programming through the use of organization blocks, function blocks, and functions. Memory Areas The processor memory area is divided into three sections. As shown in Fig. 7, each memory area stores the user program, user data, and configuration. The following is a brief description of each section: • Load memory is nonvolatile storage for the user program, data, and configuration. • Work memory is a volatile storage work area for some elements of the user project while the user program is executing. • Retentive memory is nonvolatile storage for a limited quantity of work memory values. ===== Tbl. 1 S7-1200 PLC Specifications Feature CPU 1211C CPU 1212C CPU 1214C Physical size (mm) 90 × 100 × 75 110 × 100 × 75 User memory • Work memory • Load memory • Retentive memory • 25 Kbytes • 1 Mbyte • 2 Kbytes • 50 Kbytes • 2 Mbytes • 2 Kbytes Local on-board I/O • Digital • Analog • 6 inputs/4 outputs • 2 inputs • 8 inputs/6 outputs • 2 inputs • 14 inputs/10 outputs • 2 inputs Process image size 1024 bytes (inputs) and 1024 bytes (outputs) Signal modules expansion None 2 8 Signal board 1 Communication modules 3 (left-side expansion) High-speed counters • Single phase • Quadrature phase 3 • 3 at 100 kHz • 3 at 80 kHz 4 • 3 at 100 kHz 1 at 30 kHz • 3 at 80 kHz 1 at 20 kHz 6 • 3 at 100 kHz 3 at 30 kHz • 3 at 80 kHz 3 at 20 kHz Pulse outputs 2 Memory card SIMATIC memory card (optional) Real-time clock retention time 10 days, typical/6-day minimum at 40 degrees PROFINET 1 Ethemet communication port Real math execution speed 18 ms/instruction Boolean execution speed 0.1 ms/instruction
===== File type Input I Output Q Bit memory M Data block DB Fig. 8 Memory map. Load memory Work memory Retentive memory Fig. 7 Memory areas.
===== Fig. 9 CPU memory addresses. Address type Inputs (I) Outputs (Q) Bit memories (M) Timers (DB) Counters (DB) Temporary (L) Data block (DB) Peripheral inputs (PI) Peripheral outputs (PQ) === Fig. 10 Discrete addressing format. === Memory Map The processor memory map is divided into several data files, as shown in Fig. 8, where each data file consists of an operand and tags such as inputs, outputs, and bit memory. The CPU identifies these operands based on a numerical absolute address. CPU Memory Addresses The CPU can access elements addressed in the formats shown in Fig. 9. Also shown is the detailed format for a discrete output. Other address types follow the same pattern but use different number of bits per element. Discrete Output Addressing Format Fig. 10 shows the discrete addressing format. Code Blocks The CPU supports the following types of code blocks that allow users to create an efficient modular program: • Organization blocks (OBs) define the structure of a program. • Functions (FCs) and function blocks (FBs) contain the program code that corresponds to a particular task, which can be executed frequently or as needed. • Data blocks (DBs) store the data that can be used by the different program blocks. The following are examples of Siemens programming blocks that are often used to structure and enhance the documentation of uses of ladder process-control projects: • Program-cycle OBs execute repeatedly as long as the CPU is running. OB1 is the default; others must be OB200 or greater. • Startup OBs execute one time when the operating mode of the CPU changes from STOP to RUN. All codes that need to be executed only one time, such as initialization for certain parameters or the configuration of hardware modules, should be placed in startup OBs. • Time-delay OBs execute at a specified interval after an event is configured by the start interrupt (SRT_DINT) instruction. • Cyclic-interrupt OBs execute at a specified interval. A cyclic-interrupt OB will interrupt cyclic program execution at user-defined intervals. Fig. 11 A simple function. A subroutine (also known in different programming languages as a procedure, function, routine, method, or subprogram) is a portion of code within a larger program that performs a specific task and is relatively independent of the remaining code. It is similar to the previously defined OBs and FCs for the Siemens system. A subroutine is often coded so that it can be started/called several times from different places during a single execution of the program and then branch back/return to the next instruction after the call point once its task is concluded. Examples of subroutine usage include the following: • Loading and executing a specific recipe when needed • Initializing a system startup • Performing a common calculation at different points in a program • Updating alarms and displays • Updating communication data and protocol parameters Functions are logic blocks without memory. After the function has been executed, the data in the temporary variables therefore are lost. Fig. 11 shows a simple function, and the following provides details about its initiation and coding. If TAG_IN is TRUE, the function SP_VALID is executed. The function is shown in the figure with only one network. At initiation of the function, program cyclic execution transfers to the OUT_RANGE instruction, which compares the set point (SP) to the MIN value, with tag name DS_LL and MAX value, and with tag name DS_HL. If the SP is outside the low to high limit, output energizes the tag named SP_OUTSIDE_LIMT, and the function terminates. To create a function block (FB), follow these steps, as illustrated in Fig. 12: 1. Click "Add new block." 2. Click the function block (FB). 3. Enter the name for the block. Fig. 12 Creating a function block. Fig. 13 Ladder-logic diagram network/rung. 2 Ladder-Logic Diagrams PLCs use a language called a ladder-logic program, which is similar to the line diagram used in a hardwired relay control system. Fig. 13 describes the control circuit for a ladder-logic network that is composed of three basic sections: the signal, the decision, and the action. The PLC input modules scan the input signals, and the CPU executes the ladder logic program in relation to the input status and makes a decision. The output modules update and drive all output devices. The program scan process or what is referred to as PLC events in the operating cycle are summarized in Tbl. 2. A description of each scan operation is also given. The following sections show the I/O terminal connection and describe the digital I/O addressing format. === Tbl. 2 PLC Program Scan Cycle Event in Operating Cycle; Description; Input scan; The status of each input module is read, and the input image table in the processor is updated with the information; Program scan The ladder program is executed Output scan The output image table information is transferred to the output module Communication Communication with computer and other devices takes place Processor overhead Internal housekeeping in the processor takes place, including updates of the status file and internal time base === Fig. 14 I/O hardwired connections. Fig. 15 Ladder-logic network example. 1 PLC Input/Output Terminal Connection As shown in Fig. 14(a), the input devices are connected to the input module via the hot line (L1), whereas the neutral line is connected directly to the input module. Fig. 14(b) shows the output devices wired to the output terminal module through the neutral line (L2), whereas the hot line is connected directly to the output module. Fig. 15 shows a ladder-logic network. This is very similar to the line diagram used in a hardwired relay. Every instruction is examined if TRUE (TRUE means the bit in the PLC memory assigned the value of 1). If TRUE, continuity of the rung is maintained or power flow is maintained. When all input instructions are TRUE, the output will be set to 1 (ON). The figure shows an example of such network. The network has two input elements (representing decision) and a coil (representing action), as shown previously in Fig. 13. A brief description of the three commonly used instructions will be provided in the next section. The Siemens S7-1200 system notation, hardware, and software development tools will be assumed throughout this guide and in all implemented examples and projects. 2 PLC Boolean Instructions Normally Open Contact The normally open (NO) contact is closed (ON) when the assigned bit value in memory is equal to 1 (Fig. 16). Normally open Fig. 16 Normally open contact ON. As shown in Fig. 17(a), the input device is connected to the input module through the hot line (L1), whereas neutral line is connected directly to the module. When switch SS1 is open, the instruction NO in the PLC network is FALSE (assigned bit is 0). Fig. 17(b) shows the switch in the closed position, the NO instruction in the PLC network is TRUE (assigned bit is 1), and power flows as indicated by the solid line around the instruction. Normally Closed Contact The normally closed (NC) contact is open (ON) when the assigned bit value is equal to 0 (Fig. 18). Fig. 17 Hardwired connections and the associated instruction status. Fig. 18 Normally closed contact ON. Fig. 19 Hardwired connections and associated instruction status. As shown in Fig. 19(a), the input device is connected to the input module through the hot line (L1), whereas the neutral line is connected directly to the module. When switch SS1 is open, the instruction NC in the PLC network is TRUE, and power flows through the network, as indicated by the solid line around the instruction. Fig. 19(b) shows the switch in the closed position; the NC instruction in the PLC network is FALSE, and power does not flow through the network. Fig. 20 Output-coil memory bit. Output coil ( ) Output Coil The output-coil instruction writes a value for an output bit in the PLC memory based on the power-flow status preceding the instruction; if all preceding conditions are TRUE, the output instruction becomes TRUE. The output signals for the associated control actuators are wired to the output-coil terminals. Coils are assigned unique memory bit addresses. No two coils can have the same address except for the set reset (SR) instruction, which will be discussed in the next section. The memory bit associated with the coil instruction is updated every scan of the ladder in the following manner: • If the output-coil memory bit is set to 1, then power flows through that output coil. • If the output coil memory bit is set to 0, then power will not flow through that output coil (Fig. 20). Fig. 21 shows the three instructions: normally open (NO), normally close (NC), and output coil (OC) hardwired connections in relation to the PLC instructions. Notice that when an instruction is TRUE, power flows through the instruction. 3 Shift and Rotate Instructions This section examines four of the commonly used memory-register shift and rotate instructions: the shift-right (SHR), the shift-left (SHL), the rotate-all-right (ROR), and the rotate-all-left (ROL) instructions. Each of these instructions has an IN tag and an OUT tag and enable input (EN) and enable output (ENO) connections. They each have an input N indicating the number of bits to be used for the shift or rotate operation. Fig. 21 Hardwired connections and the associated instructions status. Fig. 22 Shift-right instruction. Fig. 23 Shift-left instruction. Shift-Right Instruction (SHR) Fig. 22 shows this instruction. If TAG_IN is set, the shift right instruction is executed. The content of TAG_VALUE_IN is shifted 3 bit positions to the right. The result is sent to the TAG_VALUE_OUT output. If TAG_VALUE_IN = 0011 1111 1010 1111, then after the SHR instruction executes, the TAG_VALUE_OUT will equal 0000 0111 1111 0101. Shift-Left Instruction (SHL) Fig. 23 shows this instruction. If TAG_IN is set, the shift-left instruction is executed. The content of TAG_VALUE_IN is shifted 4 bit positions to the left, as indicated by the unsigned integer TAG_SHIFT_NUMBER, which contains the value 4. The result is sent to the TAG_VALUE_OUT output. If TAG_VALUE = 0011 1111 1010 1111, then after the instruction SHL executes, the TAG_VALUE_OUT will equal 1111 1010 1111 0000. Rotate-All-Right Instruction (ROR) Fig. 24 shows this instruction. If TAG_IN is set, the rotate all right instruction is executed. The content of TAG_VALUE_IN is rotated 5 bit positions to the right, as indicated by the unsigned integer TAG_ROR_NUMBER, which is assigned the value 5. The result is sent to the TAG_VALUE_OUT output. If TAG_VALUE_IN = 0000 1111 1001 0011, then after the ROR instruction executes, the TAG_VALUE_OUT will equal 1001 1000 0111 1100. Rotate-All-Left Instruction (ROL) Fig. 25 shows this instruction. If TAG_IN is set, the rotate all left instruction is executed. The content of TAG _VALUE_IN is rotated 5 bit positions to the right, as indicated by the constant number 5 in the TAG_ROR_NUMBER. The result is sent to the TAG_VALUE_OUT output. If TAG_VALUE_IN = 1010 1000 1111 0110, then after the ROR instruction executes, the TAG_VALUE_OUT will equal 0001 1110 1101010 1. Fig. 24 Rotate all right instruction. Fig. 25 Rotate all left instruction. 4 Program-Control Instructions This section details two of the commonly used program-control instructions. These instructions divert the processor from the sequential network scan and execution under certain conditions. These conditions are synchronous events initiated by the executing program, unlike asynchronous events such as interrupts. Jump and label, switch-jump distributor, and function calls are covered in this section. Jump and Label Instructions Program-control instructions are used to interrupt the linear execution flow of a pro gram and resume it in another network. The destination network must be identified by a jump label (LABEL). These instructions are essential because they allow program scanning and decision making to be altered according to user's predefined conditions or real-time scenarios. The screen shown in Fig. 26 illustrates the jump and label instruction and its application, as documented in the Siemens S7-1200 PLC system. If TAG_IN1 is TRUE, the JMP instruction is executed. Linear execution of the program is interrupted and resumes execution in the network labeled CASE1. If TAG_IN3 is set, output tag name TAG_OUT2 is set, whereas the network 2 TAG_OUT1 status will not update. Fig. 26 Jump and label instruction. Switch-Jump Distributor The switch-jump distributor allows program control to transfer to DEST0, DEST1, or the ELSE assigned labels. In the configured instruction in Fig. 27, we used LABEL0, LABEL1, and LABEL2 for these assignments. The user can select the =, >, or < quantifiers for each of the input tags. TAG_VALUE1 and TAG_VALUE2 are compared to the input value of TAG_VALUE. The comparison result determines whether program control goes to LABEL0, LABEL1, or LABEL2. If the TAG_INPUT is set TRUE, the switch-jump distributor instruction is executed. If TAG_VALUE is equal to TAG_VALUE1, control goes to LABEL0, which is assigned to the same network in this example (no jump occurs). If TAG_VALUE is greater than TAG_VALUE2, then program execution jumps to LABEL1 and PL1 turns ON. Otherwise, PL2 goes ON. Fig. 27 Switch-jump distributor. 3 Sequential and Combinational Logic Instructions Sequential and combinational logic instructions are discussed in this section. The set-reset (SR), the set (S), the reset (R), the positive-edge (P), and the negative-edge (N) instructions are covered. This will be followed by coverage of common combinational logic instruction with a brief review of digital-logic fundamentals. 3.1 The Set-Reset Flip-Flop Instructions The set-reset (SR) flip-flop logic is used to describe and document the LATCH and UNLATCH relay functions in the PLC. When both inputs PB1 and PB2 are at zero state, the output S is in a hold state, latching the previous output status. When PB1 is set to 1 and PB2 is reset to 0, the output S will be set to 1 (output R is reset). When PB1 is reset to 0 and PB2 is set to 1, the output S will be reset to 0 (output R is set). The state where PB1 is set to 1 and PB2 set to 1 is invalid (prohibited state for the SR flip-flop) and should not be used (hardwired switches should be interlocked). Fig. 28 shows the SR logic and PLC connections. When PB1 is pushed, it sets S to 1, and R is reset. This will cause PL to turn ON, as indicated by the shaded circle. To turn the PL OFF, PB2 should be activated/pressed. 3.2 Set and Reset Output Instructions Set-Output Instruction (S): Set 1 Bit This instruction is executed only if the preceding logic for the same network is TRUE (power flows to the S coil); then S is activated. When the preceding net work input (power flow to the coil) is FALSE, then S maintains the active status. S remains active until a reset action is executed (Fig. 29). Reset-Output Instruction (R): Reset 1 Bit This instruction is executed only if the preceding logic for the same network is TRUE (power flows to the R coil); then R is activated, which resets the S coil. When the preceding rung input (power flow to the coil) is FALSE, then S maintains the inactive status (Fig. 30). Fig. 28 Set-reset hardwired connections and instruction status. Fig. 29 Set output instruction. Fig. 30 Reset output instruction. Fig. 31 shows the timing diagram for set-reset instructions. Notice that the two signals cannot be active at the same time. The figure assumes that O represents the logic status of input to the S or R coil network. 3.3 Positive and Negative Edge Instructions Positive Edge Instruction Fig. 32 shows this instruction. The state of this contact is TRUE for one scan when a positive transition (OFF to ON) is detected on the assigned positive edge bit INPUT. Power flows in the network for one program scan from the time where a positive edge is triggered. Fig. 33 shows the timing diagram for this instruction. Fig. 31 Set and reset instructions timing diagram. Fig. 32 Positive edge instruction. Negative Edge Instruction The state of this contact is TRUE for one scan when a negative transition (ON to OFF) is detected on the assigned negative edge bit INPUT. Power flows in the network for one program scan from the time where edge is triggered. Fig. 34 shows the operation of this instruction. Fig. 33 Positive edge timing diagram. Notice that the address of the edge memory bit for the positive or the negative edge instruction must not be used more than once in the entire program; other wise, the memory bit will be overwritten. 3.4 Logic Gates and Truth Tables Digital systems logic elements are classified as combinational or sequential. The combinational logic includes AND, OR, NOT, NAND, NOR, XOR, and XNOR gates. Sequential logic instructions were covered in Sec. 2.3.3. These instructions will be used extensively throughout this guide. The basic combinational logic operations are described as follows. AND Logic Gate If all inputs are TRUE, then the output becomes TRUE; otherwise, the output is FALSE (Fig. 35). Fig. 34 Negative edge timing diagram. Fig. 35 AND logic gate. Truth tables show the output logic for all possible input logic conditions for a given gate or logic function. Tbl. 3 is the logic table for a two-input AND gate. The product sign (.) is used as the Boolean operator for AND gate operation. Tbl. 3 Truth Table for Two-Input AND Gate AND GATE LOGIC OR Logic Gate If all inputs are FALSE, then the output is FALSE; otherwise, the output is TRUE. A plus sign (+) is known as the Boolean operator for logic OR (Fig. 36). Fig. 36 OR logic gate. Tbl. 4 is the truth table for a two-input OR gate. Tbl. 4 Truth Table for a Two-Input OR Gate OR GATE LOGIC NOT Logic Gate The output of the NOT (inverter) gate is the inverse of the input logic (Fig. 37). Fig. 37 NOT logic gate. Tbl. 5 is the truth table for a NOT gate. If the input variable to the inverter is labeled A, then the inverted output is known as A NOT. This is also shown as A' or A with a bar over the top, as shown at the gate output. Tbl. 5 Truth Table for a NOT Gate NOT GATE LOGIC NAND Logic Gate If all inputs are TRUE, then the NAND gate output turns FALSE; otherwise, the output is TRUE. This is a NOT-AND gate, which is equal to an AND gate followed by a NOT gate (Fig. 38). Fig. 38 NAND logic gate. Tbl. 6 is the truth table for the NAND gate. Tbl. 6 Truth Table for a NAND Gate NAND GATE LOGIC NOR Logic Gate If all inputs are FALSE, then the NOR gate output becomes TRUE; otherwise, the gate output is FALSE (Fig. 39). Fig. 39 NOR logic gate. Tbl. 7 is the truth table for a NOR gate. This is a NOT-OR gate, which is equal to an OR gate followed by a NOT gate. Tbl. 7 Truth Table for an NOR Gate NOR GATE LOGIC XOR Logic Gate If the two inputs are of different logic levels, then the gate output becomes TRUE; otherwise, the gate output is FALSE. An inside-circle plus sign (Boolean operator) is used to show the XOR operation (Fig. 40). Fig. 40 XOR logic gate. Tbl. 8 is the truth table for an XOR gate. Tbl. 8 Truth Table for an XOR Gate XOR GATE LOGIC XNOR Logic Gate If the two inputs are the same logic level, then the gate logic output is TRUE; other wise, the gate output is FALSE. A negated sign or bar over the top of the XOR output is used to show the XNOR operation (Fig. 41). Fig. 41 XNOR logic gate. Tbl. 9 is the truth table for an XNOR gate. Tbl. 9 Truth Table for an XNOR Gate XNOR GATE LOGIC Tbl. 10 is a summary truth table of the I/O combinations for the NOT gate together with all possible I/O combinations for the other gate functions. Note that n-bit inputs have 2n rows. The names for XOR/EXOR and XNOR/EXNOR are interchangeably used in the literature. Tbl. 11 shows the symbolic representations of seven logic gates that are used to document PLC program-logic elements. Tbl. 101ogic Gate Representation Using the Truth Table Tbl. 11 Logic Gate Symbols A ladder diagram (LD) is a graphical representation of Boolean equations using contacts (inputs) and coils (outputs). The ladder-diagram language allows these features to be viewed in a graphical form by placing graphic symbols into the program workspace similar to a relay-logic electrical diagram. Both ladder diagrams and relay- logic diagrams are connected on the left sides to the power rails. 3.5 Combinational Logic Instructions Commonly used S7-12001ogic instructions are covered in this section. Please refer to the Siemens manual online for uncovered instruction or for more details. NEGATE Assignment The negate-assignment instruction inverts the result of a rung logic operation (RLO) and assigns it to the specified operand. When the RLO at the input of the coil is 1, the operand is reset. When the RLO at the input of the coil is 0, the operand is set to signal state 1. The instruction does not influence the RLO. The RLO at the input of the coil is sent directly to the output of the coil (Fig. 42). AND Logic Operation The AND logic operation ANDs 2 bytes, words, or double words at the value IN1 and IN2 inputs bit by bit and outputs the result in the OUT output. Fig. 43 shows the AND instruction. If operand Tag_IN has the signal state 1, the AND logic operation instruction is executed as shown in Tbl. 12. The value of operand Tag_Value1 and the value of operand Tag_Value2 are ANDed. The result is mapped bit for bit, and the output is placed in operand Tag_Result. Fig. 42 Negate-assignment instruction. Fig. 43 AND instruction. Tbl. 12 AND Instruction Example: Parameter Tag Name Value OR Logic Operation The OR logic operation ORs 2 bytes, words, or double words at the value IN1 and IN2 inputs bit by bit and outputs the result at the OUT output. Fig. 44 shows the OR instruction. Tbl. 13 shows how the instruction works using specific operand values. If operand Tag_IN has the signal state 1, the OR logic operation instruction is executed. The value of operand Tag_Value1 and the value of operand Tag_Value2 are ORed. The result is in Tag_Result. Tbl. 13 OR Instruction Example: Parameter Tag Name Value Fig. 44 OR instruction. XOR Logic Operation The XOR logic operation XORs 2 bytes, words, or double words at the value IN1 and IN2 inputs bit by bit and outputs the result at the OUT output. Fig. 45 shows the XOR instruction. Fig. 45 XOR instruction. If operand Tag_IN has the signal state 1, the XOR logic operation instruction is executed. The value of operands Tag_Value1 and Tag_Value2 are XORed. Tbl. 14 XOR Instruction Example: Parameter Tag Name Value The result is mapped bit for bit and output in operand Tag_Result. The operation of the OR instruction is shown in Tbl. 14 with values assigned in 2 bytes, which is equivalent to one memory word. Tbl. 15 summarizes the commonly used logic operations with the associated legend normally used in the specification and documentation of control logic. This logic legend notation will be used later in this guide in documented industrial applications. 3.6 Illustrative Ladder Examples This section presents a few implemented Siemens S7-12001adder-logic examples that illustrate the practical side of the discussions covered so far in this section. The reader is encouraged to practice these examples using a suitable training unit (similar to the one described in Fig. 29 and used in this guide) and development software. === Tbl. 15 Ladder-Logic Legend X1 Logic OR Function: If all inputs are False, output is False; otherwise output is True Xn LOGIC INVERT LOGIC LEGEND Function: Inverts input LOGIC AND Function: If all inputs are True, output is True; otherwise output is False == Example 2.1 Fig. 46 shows a ladder-logic diagram for the three instructions normally open (NO), normally closed (NC), and output coil (OC). It implements the four combinational logics AND, OR, XOR, and XNOR. This diagram assumes two input switches (SW1 and SW2) and four output coils (AND_LOGIC, OR_LOGIC, XOR_LOGIC, and XNOR_LOGIC). Fig. 46 Ladder logic for combinational logic using bit instructions. === The following is the analysis for the documented logic: • When SW1 and SW2 are closed, the NO instructions are TRUE, and power flows to the output coil (AND_LOGIC), which represents series (AND) logic. • When SW1 or SW2 or both switches are closed, the NO instructions are TRUE, and power flows to the output coil (OR_LOGIC), which represents parallel (OR) logic. • When SW1 is different from SW2, power flows to the output coil (EXOR_LOGIC), which represents the difference (XOR) logic. • When SW1 is the same as SW2, power flows to the output coil (EXNOR_LOGIC), which represents equivalence (XNOR) logic. Example 2.2 We will realize same combinational logic using word logic operations for AND, OR, XOR, and XNOR. Fig. 47 shows a ladder-logic diagram for each of the four combinational logics using single memory bytes for all inputs to the instructions. The logic shown is intended for four different programs with one network in each program. Assuming that IN1 (TAG_VALUE1) and IN2 (TAG_VALUE2) have the decimal values 2 and 3, respectively. The following is the analysis for the documented logic: • When TAG_IN is TRUE, the AND byte instruction will be executed. The OUT (TAG_RESULT), which represents AND logic, will have the decimal value 2. • When TAG_IN is TRUE, the OR byte instruction will be executed. The OUT (TAG_RESULT), which represents OR logic, will have the decimal value 3. • When TAG_IN is TRUE, the XOR byte instruction will be executed. The OUT (TAG_RESULT), which represents XOR logic, will have the decimal value 1. • When TAG_IN is TRUE, the XOR byte instruction will be executed. The invert instruction will invert the logic XOR, which is equivalent to the logic XNOR. The OUT (TAG_RESULT_XNOR) will have the decimal value -2 signed 8 bits value, which is FE hex. Example 2.3 This example will demonstrate the operation of the edge trigger instructions by illustrating the positive edge-type command. Fig. 48 shows a positive edge trigger application ladder-logic diagram. On power-up, the program initializes a reset of four memory registers. The registers are cleared one time on power-up condition. The move instruction will be detailed in Section 4. Initialization is a common task in all computer systems, which takes place during power-up, reset, or restart conditions. The edge instruction triggers one scan. Fig. 47 Combinational logic using word logic instructions. Fig. 48 Positive edge applications. Homework Problems and Laboratory Projects Problems 1 What are the main advantages of using PLCs in industrial automation? 2.2 Draw a functional block diagram of a PLC, and describe briefly the role of each component and its interface with other parts. 3 Describe the function of a PLC digital input module, digital output module, and the power supply. 4 List and explain the operating modes of PLC (CPU/processor). 5 Define the following terms: a. Program scan. b. Address c. Instruction 6 Explain how the digital input module converts 120 Vac to a low TTL voltage. Refer to Fig. 4. 7 What is the difference between the following? a. Program-cycle organizational blocks (OBs) and the startup OB b. Functions (FCs) and function blocks (FBs) 8 Explain how normally open, normally closed, and output energize instructions work. 9 What is the function of the power supply used in a PLC? 10 List the tasks performed by the CPU when the power supply is turned on? 11 Explain the difference between an output coil and the set output instruction. What reverses the status of the output in each case? 2.12 Write the Boolean equations for the following logic diagrams: a. Fig. 49 Fig. 49 b. Fig. 50 Fig. 50 13 List the conditions required to turn ON motor M for the line diagram in Fig. 51. 14 Convert the following logic diagrams into a ladder-logic program. a. Fig. 52 b. Fig. 53 15 Create a ladder-logic program for the following Boolean equation. SV = (SW1 + SW2)(SW3) where SV is a solenoid valve, and SW1, SW2, and SW3 are three ON/OFF switches. 16 Create a ladder-logic program for the following Boolean equation. (SW1.SW2)' + (SW3) = PL1 (pilot light 1) Fig. 51 Fig. 52 Fig. 53 17 For the AND word instruction in Fig. 54, complete the table for the Tag_Result word below. 18 For the OR byte instruction in Fig. 55, complete the table for the Tag_Result byte below. 19 For the XOR word instruction in Fig. 56, complete the table for the Tag_Result word below. Fig. 56 20 For the SHR word instruction in Fig. 57, complete the table for Tag_Result word below. Fig. 57 21 Repeat Problem 20 for the ROR and ROL instructions. 22 Show how you can program a network using a logic operation instruction to clear the most significant byte in memory word location MW5. 23 Show how you can program a network using a logic operation instruction to set the most significant bit in memory word location MW1. 24 Explain the set and reset output instructions, and complete the timing diagram in Fig. 58, assuming that the output (O) is initially high. 25 Explain the positive edge instruction, and complete the timing diagram in Fig. 59, assuming that the output is initially at low state. Fig. 58 Fig. 59 Fig. 60 Fig. 61 Fig. 62 Fig. 63 Fig. 64 Fig. 65 26 Show a network using bit logic instructions to implement logic NAND and logic EXCLUSIVE NOR. Projects Lab 1: Devise Configuration and Online Programming The objective of this laboratory project is to familiarize the reader with the procedures used for PLC device configuration and online programming using the S7-1200 software development portal. a. Online mode. Follow the steps for device configuration online. • From the portal view (Fig. 60) click on "Create New Project." • Enter the name of the project, and then double-click "Create" (Fig. 61). • Click "Write PLC Program" and then " Main" (Fig. 62). • From the Project View, click "Add New Device," and choose the correct PLC series from the menu (Fig. 63) • Under Catalog, choose the right digital input (DI) module (Fig. 64). The digital I/Os on the PLC processor module do not require configuration. • Under Catalog, choose the right digital output (DO) module (Fig. 65). Do not configure the I/Os on the PLC processor module. • Enter the following networks to implement the four combinational logics AND, OR, XOR, and XNOR. This diagram (Fig. 66) assumes two input switches (SW1 and SW2) and four output coils (AND_LOGIC, OR_LOGIC, EXOR_LOGIC, and EXNOR_LOGIC). b. Online viewing. In order to view and troubleshoot a program residing in PLC S7-1200 processor's memory, the programming terminal node must be communicating with the PLC processor. The following are the typical steps used in this task: • Choose Main [OB1]. • Click "Download to Device." • Push "Load" and "Finish" (Fig. 67). • Go online. • Push "Monitoring" ON/OFF (Fig. 68) • Turn on SW1 on the training unit or Siemens simulator, and monitor the logic as shown in Fig. 69. • Check out all logic using or simulating SW1 and SW2. Fig. 66 Fig. 68 Fig. 67 Fig. 69 Lab Requirements: • Use SW1 and SW2 on the training unit or the Siemens simulator to simulate the inputs for the four network logics, and confirm that the logics work. • Repeat the four logic operations using word logic instructions with 1 byte assigned to each of the two operands and the result. NOTE After adding the rest of the functions in the second requirement, your networks should look like the program in Fig. 70 but implemented using four separate functions. Notice that the same tag (TAG_RESULT) is used for all logic functions because the implemented interlock allows the user to select only one function at a time. The steps and associated screen for this laboratory are shown in Fig. 71 for only the AND instruction. Fig. 701adder combinational logic using logic instructions. Fig. 71 Fig. 72 Lab 2: Structured Programming The objective of this laboratory is to realize the combinational logic functions used in Lab 1 using word logic operations in structured programming. To create a function (FC), follow the steps illustrated in Fig. 72: • Click "Add New Block." • Click the function block (FC). • Enter the name for the block. From the Project view, follow these steps to create four functions titled AND, OR, XOR, and XNOR (Fig. 73): • Add new block. • Under Name, type "AND." • Click "Function." Repeat these steps to enter the OR, XOR, and XNOR. From the project tree, drag and drop the AND function (Fig. 74). Repeat these steps for the OR, XOR, and XNOR operations. The final organizational blocks should look as shown in Fig. 75. Lab 3: Controlling a Conveyor Belt Using Set and Reset Instructions Fig. 76 shows a conveyor belt that can be activated electrically. There are two push button switches at the beginning of the belt (Location A): S1 for start and S2 for stop. There are also two push-button switches at the end of the belt (Location B): S3 for start and S4 for stop. It is possible to start or stop the belt from either end. Lab Requirements • Assign and document all I/O addresses. • Enter the program. Fig. 73 Fig. 74 Fig. 75 "StartSwitch_Left" Network 1: The conveyor belt motor is switched on when Start switch "S1" or "S3" is pressed. S "MOTOR_ON" "StartSwitch_Right" "StartSwitch_Left" R "MOTOR_ON" "StopSwitch_Right" Network 2: The conveyor belt motor is switched off when Stop switch "S2" or "S4" is pressed. Fig. 76 • Download and go online. • Provide system check as detailed in the preceding steps. • Document your program. Lab 4: Conveyor Belt Movement Direction Fig. 77 shows a conveyor belt that is equipped with two photoelectric barriers (PEB1 and PEB2). These are designed to detect the direction in which a package is moving on the belt. Write a ladder-logic program to detect the belt movement direction. Two pilot lights (PL_R) and (PL_L) are used to indicate the direction status. Lab Requirements: • Write a ladder program to detect the conveyor movement direction and activate one of the two pilot lights. • Use positive-edge set and reset instructions to achieve the preceding task. Document your program. • Download the program to your PLC hardware or trainer, or use the Siemens simulator. Check out and debug the program. |
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Monday, March 9, 2015 18:51
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