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3. Analog to Digital Converters for Signal Conditioning
The trend in ADCs and DACs is toward higher speeds and higher resolutions at reduced power levels. Modern data converters generally operate on ±5 V (dual supply) or +5 V (single supply). In fact, many new converters operate on a single +3 V supply. This trend has created a number of design and applications problems which were much less important in earlier data converters, where ±15 V supplies and ±10 V input ranges were the standard.
Lower supply voltages imply smaller input voltage ranges, and hence more suscepti bility to noise from all potential sources: power supplies, references, digital signals, EMI/RFI, and probably most important, improper layout, grounding, and decoupling techniques. Single-supply ADCs often have an input range which is not referenced to ground. Finding compatible single-supply drive amplifiers and dealing with level shifting of the input signal in direct-coupled applications also becomes a challenge.
In spite of these issues, components are now available which allow extremely high resolutions at low supply voltages and low power. This section discusses the ap plications problems associated with such components and shows techniques for successfully designing them into systems.
The most popular precision signal conditioning ADCs are based on two fundamental architectures: successive approximation and sigma-delta. The tracking ADC archi tecture is particularly suited for resolver-to-digital converters, but it is rarely used in other precision signal conditioning applications. The flash converter and the subrang ing (or pipelined) converter architectures are widely used where sampling frequencies extend into the megahertz and hundreds of megahertz region, but are overkills in both speed and cost for low frequency precision signal conditioning applications.
¦ Typical Supply Voltages: ±5V, +5V, +5/+3V, +3V
¦ Lower Signal Swings Increase Sensitivity to all Types of Noise (Device, Power Supply, Logic, etc.)
¦ Device Noise Increases at Low Currents
¦ Common Mode Input Voltage Restrictions
¦ Input Buffer Amplifier Selection Critical
¦ Auto-Calibration Modes Desirable at High Resolutions
FIG. 3.1: Low power, low voltage ADC design issues.
¦ Successive Approximation
-- Resolutions to 16-bits
- Minimal Throughput Delay Time
-- Used in Multiplexed Data Acquisition Systems
¦ Sigma-Delta
-- Resolutions to 24-bits
-- Excellent Differential Linearity
-- Internal Digital Filter, Excellent AC Line Rejection
-- Long Throughput Delay Time
-- Difficult to Multiplex Inputs Due to Digital Filter
Settling Time
¦ High Speed Architectures:
-- Flash Converter
-- Subranging or Pipelined
FIG. 3.2: ADCs for signal conditioning.
Successive Approximation ADCs
The successive approximation ADC has been the mainstay of signal conditioning for many years. Recent design improvements have extended the sampling frequency of these ADCs into the megahertz region. The use of internal switched capacitor techniques along with auto calibration techniques extend the resolution of these ADCs to 16-bits on standard CMOS processes without the need for expensive thin-film laser trimming.
The basic successive approximation ADC is shown in FIG. 3.3. It performs conversions on command. On the assertion of the CONVERT START command, the sample-and-hold (SHA) is placed in the hold mode, and all the bits of the successive approximation register (SAR) are reset to "0" except the MSB which is set to "1". The SAR output drives the internal DAC. If the DAC output is greater than the analog input, this bit in the SAR is reset, otherwise it is left set. The next most significant bit is then set to "1". If the DAC output is greater than the analog input, this bit in the SAR is reset, otherwise it is left set. The process is repeated with each bit in turn. When all the bits have been set, tested, and reset or not as appropriate, the contents of the SAR correspond to the value of the analog input, and the conversion is complete.
FIG. 3.3: Successive approximation ADC.
[...] age on the capacitor array. Switch SC is then opened allowing the voltage at node A to move as the bit switches are manipulated. If S1, S2, S3, and S4 are all connected to ground, a voltage equal to -AIN appears at node A. Connecting S1 to VREF adds a volt age equal to VREF/2 to -AIN. The comparator then makes the MSB bit decision, and the SAR either leaves S1 connected to VREF or connects it to ground depending on the comparator output (which is high or low depending on whether the voltage at node A is negative or positive, respectively). A similar process is followed for the remaining two bits. At the end of the conversion interval, S1, S2, S3, S4, and SIN are connected to AIN, SC is connected to ground, and the converter is ready for another cycle.
Note that the extra LSB capacitor (C/4 in the case of the 3-bit DAC) is required to make the total value of the capacitor array equal to 2C so that binary division is accomplished when the individual bit capacitors are manipulated.
The operation of the capacitor DAC (cap DAC) is similar to an R/2R resistive DAC. When a particular bit capacitor is switched to VREF, the voltage divider created by the bit capacitor and the total array capacitance (2C) adds a voltage to node A equal to the weight of that bit. When the bit capacitor is switched to ground, the same voltage is subtracted from node A.
Because of their popularity, successive approximation ADCs are available in a wide variety of resolutions, sampling rates, input and output options, package styles, and costs. It would be impossible to attempt to list all types, but FIG. 3.5 shows a number of recent Analog Devices' SAR ADCs which are representative. Note that many devices are complete data acquisition systems with input multiplexers which allow a single ADC core to process multiple analog channels.
FIG. 3.5: Resolution/conversion time comparison for representative
single-supply SAR ADCs.
While there are some variations, the fundamental timing of most SAR ADCs is similar and relatively straightforward (see FIG. 3.6). The conversion process is initiated by asserting a CONVERT START signal. The CONVST signal is a negative going pulse whose positive-going edge actually initiates the conversion. The internal sample-and-hold (SHA) amplifier is placed in the hold mode on this edge, and the various bits are determined using the SAR algorithm. The negative-going edge of the CONVST pulse causes the EOC or BUSY line to go high. When the conversion is complete, the BUSY line goes low, indicating the completion of the conversion process. In most cases the trailing edge of the BUSY line can be used as an indication that the output data is valid and can be used to strobe the output data into an external register. However, because of the many variations in terminology and design, the individual data sheet should always be consulted when using with a specific ADC.
It should also be noted that some SAR ADCs require an external high frequency clock in addition to the CONVERT START command. In most cases, there is no need to synchronize the two. The frequency of the external clock, if required, generally falls in the range of 1 MHz to 30 MHz depending on the conversion time and resolution of the ADC. Other SAR ADCs have an internal oscillator which is used to perform the conversions and only require the CONVERT START command. Because of their architecture, SAR ADCs allow single-shot conversion at any repetition rate from DC to the converter's maximum conversion rate.
In a SAR ADC, the output data for a particular cycle is valid at the end of the con version interval. In other ADC architectures, such as sigma-delta or the two- stage subranging architecture shown in FIG. 3.7, this is not the case. The subranging ADC shown in the figure is a two-stage pipelined or subranging 12-bit converter.
The first conversion is done by the 6-bit ADC which drives a 6-bit DAC. The out put of the 6-bit DAC represents a 6-bit approximation to the analog input. Note that SHA2 delays the analog signal while the 6-bit ADC makes its decision and the 6-bit DAC settles. The DAC approximation is then subtracted from the analog signal from SHA2, amplified, and digitized by a 7-bit ADC. The outputs of the two conversions are combined, and the extra bit used to correct errors made in the first conversion.
The typical timing associated with this type of converter is shown in FIG. 3.8.
FIG. 3.6: Typical SAR ADC timing.
FIG. 3.7: 12-bit two-stage pipelined ADC architecture.
FIG. 3.8: Typical pipelined ADC timing.
Note that the output data presented immediately after sample X actually corresponds to sample X-2, i.e., there is a two clock-cycle "pipeline" delay. The pipelined ADC architecture is generally associated with high speed ADCs, and in most cases the pipeline delay, or latency, is not a major system problem in most applications where this type of converter is used.
Pipelined ADCs may have more than two clock-cycles latency depending on the particular architecture. For instance, the conversion could be done in three, or four, or perhaps even more pipelined stages causing additional latency in the output data.
Therefore, if the ADC is to be used in an event-triggered (or single-shot) mode where there must be a one-to-one time correspondence between each sample and the corresponding data, then the pipeline delay can be troublesome, and the SAR architecture is advantageous. Pipeline delay or latency can also be a problem in high speed servo-loop control systems or multiplexed applications. In addition, some pipelined converters have a minimum allowable conversion rate and must be kept running to prevent saturation of internal nodes.
Switched capacitor SAR ADCs generally have unbuffered input circuits similar to the circuit shown in FIG. 3.9 for the AD7858/59 ADC. During the acquisition time, the analog input must charge the 20 pF equivalent input capacitance to the correct value. If the input is a DC signal, then the source resistance, RS, in series with the 125 ohm internal switch resistance creates a time constant. In order to settle to 12-bit ac curacy, approximately 9 time constants must be allowed for settling, and this defines the minimum allowable acquisition time.
(Settling to 14-bits requires about 10 time constants, and 16-bits requires about 11).
TACQ > 9 × (RS + 125) ohm × 20 pF.
For example, if RS = 50 ohm, the acquisition time per the above formula must be at least 310 ns.
For AC applications, a low impedance source should be used to prevent distortion due to the non-linear ADC input circuit. In a single supply application, a fast settling rail-to-rail op amp such as the AD820 should be used. Fast settling allows the op amp to settle quickly from the transient currents induced on its input by the internal ADC switches. In FIG. 3.9, the AD820 drives a lowpass filter consisting of the 50 ohm series resistor and the 10 nF capacitor (cutoff frequency approximately 320 kHz). This filter removes high frequency components which could result in aliasing and increased noise.
FIG. 3.9: Driving switched capacitor inputs of AD7858/59 12-bit, 200
kSPS ADC.
Using a single supply op amp in this application requires special consideration of sig nal levels. The AD820 is connected in the inverting mode and has a signal gain of -1.
The noninverting input is biased at a common mode voltage of +1.3 V with the 10.7 k-ohm /10 k-ohm divider, resulting in an output voltage of +2.6 V for VIN = 0 V, and +0.1 V for VIN = +2.5 V. This offset is provided because the AD820 output cannot go all the way to ground, but is limited to the VCESAT of the output stage NPN transistor, which under these loading conditions is about 50 mV. The input range of the ADC is also offset by +100 mV by applying the +100mV offset from the 412 ohm/10 k-ohm divider to the AIN- input.
The AD789X-family of single supply SAR ADCs (as well as the AD974, AD976, and AD977) includes a thin film resistive attenuator and level shifter on the analog input to allow a variety of input range options, both bipolar and unipolar. A simplified diagram of the input circuit of the AD7890-10 12-bit, 8-channel ADC is shown in FIG. 3.10. This arrangement allows the converter to digitize a ±10V input while operating on a single +5 V supply. The R1/R2/R3 thin film network provides the attenuation and level shifting to convert the ±10 V input to a 0 V to +2.5 V signal which is digitized by the internal ADC. This type of input requires no special drive circuitry because R1 isolates the input from the actual converter circuitry. Nevertheless, the source resistance, RS, should be kept reasonably low to prevent gain errors caused by the RS/R1 divider.
FIG. 3.10: Driving single-supply ADCs with scaled inputs.
FIG. 3.12: Simplified diagram of a typical analog multiplexer.
FIG. 3.11: Basic CMOS analog switch.
SAR ADCs with Multiplexed Inputs
Multiplexing is a fundamental part of many data acquisition systems, and a fundamental understanding of multiplexers is required to design a data acquisition system.
Switches for data acquisition systems, especially when integrated into the IC, generally are CMOS-types shown in FIG. 3.11. Utilizing the P-Channel and N-Channel MOSFET switches in parallel minimizes the change of on-resistance (RON) as a function of signal voltage. On-resistance can vary from less than 5 ohm to several hundred ohms depending upon the device. Variation in on-resistance as a function of signal level (often called RON-modulation) can cause distortion if the multiplexer must drive a load, and therefore RON flatness is also an important specification.
Because of non-zero RON and RON-modulation, multiplexer outputs should be isolated from the load with a suitable buffer amplifier. A separate buffer is not required if the multiplexer drives a high input impedance, such as a PGA, SHA or ADC--but be ware! Some SHAs and ADCs draw high frequency pulse current at their sampling rate and cannot tolerate being driven by an unbuffered multiplexer.
The key multiplexer specifications are switching time, on-resistance, on resistance flatness, and off-channel isolation, and crosstalk. Multiplexer switching time ranges from less than 20 ns to over 1µs, RON from less than 5 ohm to several hundred ohms, and off channel isolation from 50 to 90 dB.
A number of CMOS switches can be connected to form a multiplexer as shown in FIG. 3.12. The number of input channels typically ranges from 4 to 16, and some multiplexers have internal channel-address decoding logic and registers, while with others, these functions must be performed externally. Unused multiplexer inputs must be grounded or severe loss of system accuracy may result.
Complete Data Acquisition Systems on a Chip
VLSI mixed-signal processing allows the integration of large and complex data acquisition circuits on a single chip. Most signal conditioning circuits including multiplexers, PGAs, and SHAs, can now be manufactured on the same chip as the ADC. This high level of integration permits data acquisition systems (DASs) to be specified and tested as a single complex function.
Such functionality relieves the designer of most of the burden of testing and calcu lating error budgets. The DC and AC characteristics of a complete data acquisition system are specified as a complete function, which removes the necessity of calculat ing performance from a collection of individual worst case device specifications. A complete monolithic system should achieve a higher performance at much lower cost than would be possible with a system built up from discrete functions. Furthermore, system calibration is easier, and in fact many monolithic DASs are self calibrating, offering both internal and system calibration functions.
The AD7858 is an example of a highly integrated IC DAS (see FIG. 3.13). The device operates on a single supply voltage of +3 V to +5.5 V and dissipates only 15 mW. The resolution is 12-bits, and the maximum sampling frequency is 200 kSPS. The input multiplexer can be configured either as eight single-ended inputs or four pseudo-differential inputs. The AD7858 requires an external 4 MHz clock and initi ates the conversion on the positive-going edge of the CONVST pulse which does not need to be synchronized to the high frequency clock. Conversion can also be initiated via software by setting a bit in the proper control register.
FIG. 3.13: AD7858 12-bit, 200 kSPS 8-channel single-supply ADC.
The AD7858 contains an on-chip 2.5 V reference (which can be overridden with an external one), and the fullscale input voltage range is 0 V to VREF. The internal DAC is a switched capacitor type, and the ADC contains a self-calibration and system calibration option to ensure accurate operation over time and temperature. The input/ output port is a serial one and is SPI, QSPI, 8051, and µP compatible.
The AD7858L is a lower power (5.5 mW) version of the AD7858 which operates at a maximum sampling rate of 100 kSPS.
Sigma-Delta (Sigma-Delta ) Measurement ADCs
Sigma-delta analog-digital converters (Sigma-Delta ADCs) have been known for nearly thirty years, but only recently has the technology (high-density digital VLSI) existed to manufacture them as inexpensive monolithic integrated circuits. They are now used in many applications where a low-cost, low-bandwidth, low-power, high-resolution ADC is required.
There have been innumerable descriptions of the architecture and theory of Sigma-Delta ADCs, but most commence with a maze of integrals and deteriorate from there. In the Applications Department at Analog Devices, we frequently encounter engineers who do not understand the theory of operation of Sigma-Delta ADCs and are convinced, from study of a typical published article, that it is too complex to comprehend easily.
There is nothing particularly difficult to understand about Sigma-Delta ADCs, as long as you avoid the detailed mathematics, and this section has been written in an attempt to clarify the subject. A Sigma-Delta ADC contains very simple analog electronics (a comparator, a switch, and one or more integrators and analog summing circuits), and quite complex digital computational circuitry. This circuitry consists of a digital signal processor (DSP) which acts as a filter (generally, but not invariably, a low pass filter). It is not necessary to know precisely how the filter works to appreciate what it does. To understand how a Sigma-Delta ADC works, familiarity with the concepts of over-sampling, quantization noise shaping, digital filtering, and decimation is required.
FIG. 3.14: Sigma-delta ADCs.
¦ Low Cost, High Resolution (to 24-bits) Excellent DNL,
¦ Low Power, but Limited Bandwidth
¦ Key Concepts are Simple, but Math is Complex
-- Oversampling
-- Quantization Noise Shaping
-- Digital Filtering
-- Decimation
¦ Ideal for Sensor Signal Conditioning
-- High Resolution
-- Self, System, and Auto Calibration Modes
Let us consider the technique of over-sampling with an analysis in the frequency domain. Where a DC conversion has a quantization error of up to ½ LSB, a sampled data system has quantization noise. A perfect classical N-bit sampling ADC has an RMS quantization noise of q/v12 uniformly distributed within the Nyquist band of DC to fs/2 (where q is the value of an LSB and fs is the sampling rate) as shown in FIG. 3.15A. Therefore, its SNR with a full-scale sinewave input will be (6.02N + 1.76) dB. If the ADC is less than perfect, and its noise is greater than its theoretical mini mum quantization noise, then its effective resolution will be less than N-bits. Its actual resolution (often known as its effective number of bits or ENOB) will be defined by
ENOB = [SNR - 1.76 dB] / 6.02 dB
If we choose a much higher sampling rate, Kfs (see FIG. 3.15B), the quantization noise is distributed over a wider bandwidth DC to Kfs/2. If we then apply a digital low pass filter (LPF) to the output, we remove much of the quantization noise, but do not affect the wanted signal-so the ENOB is improved. We have accomplished a high resolution A/D conversion with a low resolution ADC. The factor K is generally referred to as the oversampling ratio.
Since the bandwidth is reduced by the digital output filter, the output data rate may be lower than the original sampling rate (Kfs) and still satisfy the Nyquist criterion. This may be achieved by passing every Mth result to the output and discarding the remainder. The process is known as "decimation" by a factor of M. Despite the origins of the term (decem is Latin for ten), M can have any integer value, provided that the output data rate is more than twice the signal bandwidth. Decimation does not cause any loss of information (see FIG. 3.15B).
If we simply use over-sampling to improve resolution, we must over-sample by a factor of 22N to obtain an N-bit increase in resolution. The Sigma-Delta converter does not need such a high over-sampling ratio because it not only limits the signal passband, but also shapes the quantization noise so that most of it falls outside this passband as shown in FIG. 3.15C.
FIG. 3.15: Oversampling, digital filtering, noise shaping, and decimation.
If we take a 1-bit ADC (generally known as a comparator), drive it with the output of an integrator, and feed the integrator with an input signal summed with the output of a 1-bit DAC fed from the ADC output, we have a first-order Sigma-Delta modulator as shown in FIG. 3.16. Add a digital low pass filter (LPF) and decimator at the digital output, and we have a Sigma-Delta ADC: the Sigma-Delta modulator shapes the quantization noise so that it lies above the passband of the digital output filter, and the ENOB is therefore much larger than would otherwise be expected from the over-sampling ratio.
Intuitively, a Sigma-Delta ADC operates as follows. Assume a DC input at VIN. The integrator is constantly ramping up or down at node A. The output of the comparator is fed back through a 1-bit DAC to the summing input at node B. The negative feedback loop from the comparator output through the 1-bit DAC back to the summing point will force the average DC voltage at node B to be equal to VIN. This implies that the average DAC output voltage must equal to the input voltage VIN. The average DAC output voltage is controlled by the ones-density in the 1-bit data stream from the comparator output. As the input signal increases towards +VREF , the number of "ones" in the serial bit stream increases, and the number of "zeros" decreases. Similarly, as the signal goes negative towards -VREF , the number of "ones" in the serial bit stream decreases, and the number of "zeros" increases. From a very simplistic standpoint, this analysis shows that the average value of the input voltage is contained in the serial bit stream out of the comparator. The digital filter and decimator process the serial bit stream and produce the final output data.
The concept of noise shaping is best explained in the frequency domain by considering the simple Sigma-Delta modu lator model in FIG. 3.17.
FIG. 3.16: First order sigma-delta ADC.
FIG. 3.17: Simplified frequency domain linearized model of a sigma-delta
modulator.
FIG. 3.18: Sigma-delta modulators shape quantization noise.
The integrator in the modulator is represented as an analog lowpass filter with a transfer function equal to H(f) = 1/f. This transfer function has an amplitude response which is inversely proportional to the input frequency. The 1-bit quantizer generates quantization noise, Q, which is injected into the output summing block. If we let the input signal be X, and the output Y, the signal coming out of the input summer must be X - Y. This is multiplied by the filter transfer function, 1/f, and the result goes to one input to the output summer. By inspection, we can then write the expression for the output voltage Y as:
This expression can easily be rearranged and solved for Y in terms of X, f, and Q:
Note that as the frequency f approaches zero, the output voltage Y approaches X with no noise component. At higher frequencies, the amplitude of the signal component decreases, and the noise component increases. At high frequency, the output consists primarily of quantization noise. In essence, the analog filter has a lowpass effect on the signal, and a highpass effect on the quantization noise. Thus the analog filter per forms the noise shaping function in the Sigma-Delta modulator model.
For a given input frequency, higher order analog filters offer more attenuation. The same is true of Sigma-Delta modulators, provided certain precautions are taken.
By using more than one integration and summing stage in the Sigma-Delta modulator, we can achieve higher orders of quan tization noise shaping and even better ENOB for a given over-sampling ratio as is shown in FIG. 3.18 for both a first and second-order Sigma-Delta modulator.
The block diagram for the second-order Sigma-Delta modulator is shown in FIG. 3.19.
Third, and higher, order Sigma-Delta ADCs were once thought to be potentially unstable at some values of input. Recent analyses using finite rather than infinite gains in the comparator have shown that this is not necessarily so, but even if instability does start to occur, it is not important, since the DSP in the digital filter and decimator can be made to recognize incipient instabil ity and react to prevent it.
FIG. 3.20 shows the relationship between the order of the Sigma-Delta modula tor and the amount of over-sampling necessary to achieve a particular SNR. For instance, if the oversampling ratio is 64, an ideal second-order system is capable of providing an SNR of about 80dB. This implies approximately 13 effective number of bits (ENOB). Al though the filtering done by the digital filter and decimator can be done to any degree of precision desirable, it would be pointless to carry more than 13 binary bits to the outside world. Addi tional bits would carry no useful signal information, and would be buried in the quantization noise unless post-filtering techniques were employed.
FIG. 3.19: Second-order sigma-delta ADC.
FIG. 3.20: SNR versus oversampling ratio for first, second, and third-order
loops.
The Sigma-Delta ADCs that we have described so far contain integrators, which are low pass filters, whose passband extends from DC. Thus, their quanti zation noise is pushed up in frequency. At present, most commercially available Sigma-DeltaADCs are of this type (although some which are intended for use in audio or tele communications applications contain bandpass rather than lowpass digital filters to eliminate any system DC offsets). Sigma-delta ADCs are available with resolutions up to 24-bits for DC measurement applications (AD77XX-family), and with resolu tions of 18-bits for high quality digital audio applications (AD1879).
But there is no particular reason why the filters of the Sigma-Delta modulator should be LPFs, except that traditionally ADCs have been thought of as being baseband devices, and that integrators are somewhat easier to construct than bandpass filters. If we replace the integrators in a Sigma-Delta ADC with bandpass filters (BPFs), the quantization noise is moved up and down in frequency to leave a virtually noise-free region in the pass band (see Reference 1). If the digital filter is then programmed to have its pass-band in this region, we have a Sigma-Delta ADC with a bandpass, rather than a lowpass characteristic. Although studies of this architecture are in their infancy, such ADCs would seem to be ideally suited for use in digital radio receivers, medical ultrasound, and a num ber of other applications.
A Sigma-Delta ADC works by over-sampling, where simple analog filters in the Sigma-Delta modula tor shape the quantization noise so that the SNR in the bandwidth of interest is much greater than would otherwise be the case, and by using high performance digital filters and decimation to eliminate noise outside the required passband. Because the analog circuitry is so simple and undemanding, it may be built with the same digital VLSI process that is used to fabricate the DSP circuitry of the digital filter. Because the basic ADC is 1-bit (a comparator), the technique is inherently linear.
Although the detailed analysis of Sigma-Delta ADCs involves quite complex mathematics, their basic design can be understood without the necessity of any mathematics at all. For further discussion on Sigma-Delta ADCs, refer to References 2 and 3.
High Resolution, Low-Frequency Sigma-Delta Measurement ADCs
The AD7710, AD7711, AD7712, AD7713, and AD7714, AD7730, and AD7731 are members of a family of sigma-delta converters designed for high accuracy, low frequency measurements. They have no missing codes to 24-bits, and their effective resolutions extend to 22.5 bits depending upon the device, update rate, programmed filter bandwidth, PGA gain, post-filtering, etc. They all use similar sigma-delta cores, and their main differences are in their analog inputs, which are optimized for different transducers. Newer members of the family, such as the AD7714, AD7730/7730L, and the AD7731/7731L are designed and specified for single supply operation.
There are also similar 16-bit devices available (AD7705, AD7706, AD7715) which also operate on single supplies.
The AD1555/AD1556 is a 24-bit two-chip Sigma-Delta modulator/filter specifically designed for seismic data acquisition systems. This combination yields a dynamic range of 120 dB. The AD1555 contains a PGA and a 4th-order Sigma-Delta modulator. The AD1555 outputs a serial 1-bit data stream to the AD1556 which contains the digital filter and decimator.