Timing Analysis and Simulation for Signal Integrity Engineers
by: Greg Edlund
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Every day, companies call upon their signal integrity engineers to make difficult decisions about design constraints and timing margins. Can I move these wires closer together? How many holes can I drill in this net? How far apart can I place these chips? Each design is unique: there?s no single recipe that answers all the questions. Today?s designs require ever greater precision, but design guides for specific digital interfaces are by nature conservative. Now, for the first time, there?s a complete guide to timing analysis and simulation that will help you manage the tradeoffs between signal integrity, performance, and cost. Writing from the perspective of a practicing SI engineer and team lead, Greg Edlund of IBM presents deep knowledge and quantitative techniques for making better decisions about digital interface design. Edlund shares his insights into how and why digital interfaces fail, revealing how fundamental sources of pathological effects can combine to create fault conditions. You won?t just learn Edlund?s expert techniques for avoiding failures: you?ll learn how to develop the right approach for your own projects and environment. Coverage includes ? Systematically ensure that interfaces will operate with positive timing margin over the product?s lifetime?without incurring excess cost ? Understand essential chip-to-chip timing concepts in the context of signal integrity ? Collect the right information upfront, so you can analyze new designs more effectively ? Review the circuits that store information in CMOS state machines?and how they fail ? Learn how to time common-clock, source synchronous, and high-speed serial transfers ? Thoroughly understand how interconnect electrical characteristics affect timing: propagation delay, impedance profile, crosstalk, resonances, and frequency-dependent loss ? Model 3D discontinuities using electromagnetic field solvers ? Walk through four case studies: coupled differential vias, land grid array connector, DDR2 memory data transfer, and PCI Express channel ? Appendices present a refresher on SPICE modeling and a high-level conceptual framework for electromagnetic field behavior Objective, realistic, and practical, this is the signal integrity resource engineers have been searching for. Preface xiii Acknowledgments xvi About the Author xix About the Cover xx Chapter 1: Engineering Reliable Digital Interfaces 1 Chapter 2: Chip-to-Chip Timing 13 Chapter 3: Inside IO Circuits 39 Chapter 4: Modeling 3D Discontinuities 73 Chapter 5: Practical 3D Examples 101 Chapter 6: DDR2 Case Study 133 Chapter 7: PCI Express Case Study 175 Appendix A: A Short CMOS and SPICE Primer 209 Appendix B: A Stroll Through 3D Fields 219 Endnotes 233 Index 235
Preface My first assignment as a signal integrity engineer was to determine the bond wire signal-to-return ratio for a group of ASICs that would go into a supercomputer IO subsystem. This seemed like a daunting task at the time (it still does) because the answer to the question seemed to depend on so many other things: receiver input thresholds, crosstalk from several sources, timing between various noise events, and clock arrival at the receiving flip-flop, to name just a few. I asked the company librarian to help me with a literature search and found that most of the good papers on the topic of margins came from a small group of engineers who worked for IBM Corp. and Digital Equipment Corp. Little did I know at the time that I would have the good fortune to work with some of these engineers later in my career. Now it's my turn to spice up this well-established body of knowledge with some contemporary examples flavored by my own unique experiences. I hope this book provides insights that will help you make the tough decisions you face in your daily work. We can talk about intersymbol interference and simultaneous switching noise until the cows come home, but the million-dollar question has always been, "How much intersymbol interference will an interface tolerate before the system crashes?." (Insert your own favorite effect in place of intersymbol interference.) Early in my career, I looked for a neat formula that would answer this question for me, but I gradually came to realize that the answers were as unique as each new design, each engineer's mind, and even a company's corporate DNA. Perhaps the ambiguity explains why folks are reluctant to discuss the topic. Nevertheless, that is exactly what I intend to do. Rather than attempt to give you a 250-page recipe for how to design your next digital interface, which my employer would not be happy about anyhow, I have tried to uncover what I see as the fundamental sources of failure and convey my own philosophy for preventing these failures from occurring. My challenge to you, the reader, is to use this book to develop your own unique approach to solving these core problems. No doubt as you're reading, you will think to yourself, "I could improve on that." After all, we are engineers. When you find mistakes (and I know you will), I hope you take them in the spirit of the book, which is communication between practicing engineers. Chapter 1, "Engineering Reliable Digital Interfaces," is a bit of a lark. I cooked up a story to illustrate the multi-faceted nature of design for signal integrity. You will probably recognize a not-so-thinly-veiled element of realism in this introduction to the book. I wrap up this short chapter with a list of information that I collect during the early stages of a design to help me make decisions on the analysis required for a new card, board, or system design. Chapter 2, "Chip-to-Chip Timing," covers the circuits used to store information in a CMOS state machine and how they fail. A set of SPICE simulations and spreadsheet budgets introduces the common-clock architecture, the first of three paradigms for transferring digital signals between chips. Even though the source-synchronous and high-speed serial paradigms are more prevalent in contemporary systems, the common-clock architecture is not dead yet. A solid approach for timing common-clock transfers is a useful thing to have in the toolbox. IO circuits play a pivotal role in signal integrity engineering, yet we seldom get to lay our eyes on a schematic for one of them. A handful of CMOS IO circuits get used time and again, and Chapter 3, "Inside IO Circuits," examines their pertinent electrical characteristics. It also covers the assumptions we make when using behavioral models for these circuits. Studying these circuits provides a basis for understanding the more esoteric circuits. In this chapter and throughout the book, I make repeated references to the accuracy and quality of the models we use in signal integrity simulations. Modeling forms the core of this book?both component modeling and interface modeling. It is essential to have a solid grip on the assumptions behind the models before stating that you trust the results of your simulations. Toward that end, Chapters 4, "Modeling 3D Discontinuities," and 5, "Practical 3D Field Examples," discuss the topic of 3D electromagnetic modeling in a manner that I hope will be digestible to the newcomer. Be advised that you may need to read them more than once because field solvers are simply not as familiar to us as SPICE or IBIS. Both chapters are suitable for someone just getting started in 3D electromagnetic modeling and for those who want to ask their model providers the tough questions. Chapters 6, "DDR2 Case Study," and 7, "PCI Express Case Study," tackle that million-dollar question: Will an interface operate with positive timing margin over the lifetime of the product without incurring the high costs associated with excessive conservatism? Here is where engineering can begin to lapse into religious fervor, mostly for lack of data. I have never been a big fan of throwing all the models into a pot, stirring it around, and taking a taste. My approach involves picking apart each interface piece by piece?understanding how many mV of crosstalk a connector generates and how many ps of eye closure go along with it. We owe it to our colleagues to show them our numbers and hope they will reciprocate. It's the only way to weed out the natural tendency toward covering one's own backside. Only when the numbers are on the table can you have a decent, meaningful argument. For those new to signal integrity or simply in need of a refresher, Appendix A, "A Short CMOS and SPICE Primer," touches on some basic CMOS circuits and how we model them in SPICE. When you're sitting in a class on electromagnetic theory, it's easy to get tangled up in vector calculus and lose sight of the physics. Appendix B, "A Stroll Through 3D Fields," hangs a high-level conceptual framework for field behavior. Think of it as a 5,000-foot flight over the scenery that attempts to place the physics in the context of engineering. The people who will benefit the most from this book are new signal integrity engineers, those in transition from another discipline, and university students. Occasionally, I even run across the seasoned signal integrity engineer who has not had much exposure to chip-to-chip timing for whatever reason?well, more than occasionally. Because this is not a text on signal theory, I assume you have access to the other fine books on the market and can refer to them for concepts I do not develop here.
Reviews:
f you are new to the simulation world (apart from some basic SPICE in college) with words like IBIS models, 3D EM simulation being new to you then this is an excellent book to start. If you are already experienced in the simulation area and looking for an advanced book this is not it.
Superb intro to timing analysis/simulation for SI engineers who just joined the field: Most current SI books focus on explaining the origin and the modeling of electrical phenomena on PCBs, but barely address the practical but important question of how to systematically assess the impact of these phenomena and a host of other issues on the system timing budget. Issues such as: Read/Write timing, impedance tolerance, pin-to-pin capacitance variation, DIMM connector crosstalk, Vref AC noise and resistor tolerance, slope derating factor, etc. This is not a from-A-to-Z cook book where you just blindly follow a set of instructions, but rather a collection of insights and experiences in dealing with these issues in the author's career that he has distilled into a systematic checklist for assessing the "heath" of the system timing in the midst of all of these budget timing corruptors. The 2 (substantial) case studies of DDR2 and PCI Express interfaces give reader solid examples of how an SI engineer may want to systematically go about doing his job. It is also interesting to note that the author also points out that all problems that prevent SI engineers from doing a good job are not necessarily always technical in nature. How do you deal with a vendor that is reluctant to provide you with quality IBIS models ? Well, you will find a (good) solution to this problem in the book, too. I am an electrical engineer who is in the process of making the transition from on-chip device/circuit modeling to the challenging world of off-chip signal integrity. I have found this book filled with fundamental technical knowledge about system timing that a new comer to the field of SI should know, practical advices, sound investigation strategies, and real-life examples that I can learn from and apply in my daily work.