AMAZON multi-meters discounts AMAZON oscilloscope discounts
4. END INPUT/OUTPUT MEDIUM
Most of the noise in computer installation is due to the writing and reading actions of I/O units. Fig. 18 shows some of the typical I/O for direct user data interaction.
Fig. 18 Typical I/O arrangement
The most widely used medium for data entry is the punched card. A hole punched on the card represents the binary value 1 and the hollerith code is used for data processing.
Typical card size has dimensions of 7 3/8" long, 3 1/2" width and 0.007" thick. Each card has 80 vertical columns and there are 12 horizontal rows. Most of the program inputs used this medium and the languages like Fortran and COBOL adopted their own card formats for usage. This still is a powerful I/O unit with mainly the batch processing machines. Each card is called a unit record. The card punch also prints the characters punched into a card on the face of the card itself. Card reading operation is shown in Fig. 19.
Fig. 19 Card reading operation
The cards are stacked in the read hopper and are drawn from it one at a time. Each card passes under the read heads which are either brushes or photocells. The data read are stored in flip-flops which form the input storage register. The cards then pass over the rollers and are placed in the stacker. There is quite often a second read head which reads the data a second time to provide a validity check on the reading process. These are quite inexpensive offering a slow speed of 100 to 1000 cards per minute. In early machines, the job control cards have to be fed along with the program deck when operating systems were in their infancy. Card punching units are available for a faster store of the output data from the computer system. These also serve as permanent back-up store on selective data security systems besides employed in real-time categories. This card device is treated more today as an OFF-line store. The ASCII and EBCDIC are the usual alphanumeric codes applied with these units.
The paper tape is continuous reel of storage like a magnetic tape which is also used as input/output data mainly in dedicated slow real time processes like numerical control of machine tools. The coding and reading becomes embedded onto such systems.
Also printers are used for outputting with varying speeds (character at a time to line at a time types) belong to the electromechanical category of I/O medium.
Computer Printouts
The throughput of a Computer is measured by the printed output produced during frequent intervals of time period. The speed and quality of printing are essential component" today, for printers are the primary output devices used to prepare documents in human-readable form (hard copy). Impact printers use the familiar typewriter approach of hammering a typeface against paper and inked ribbon, while non-impact printers use thermal, electrostatic. Chemical and inkjet technologies. In what follows, different printers are discussed.
Character Printers
These print only one character at a time. Letter-quality printers use a daisy wheel as a printwheel font.
Each petal of the daisy wheel has a character embossed on it. A motor spins the wheel at a rapid rate. When the desired character spins to the correct position, a print hammer stokes it to produce the output. The speed ranges from 10 to 50 characters per second.
Dot Matrix Printers
These print each character as a pattern of dots (9 x 7 matrix). Seven rows with nine needles in each.
The shape of each character, i.e., the dot pattern is obtained from information held electronically in the printer. The speed ranges from 40 to 250 characters per second used with micro-computer systems. The flexibility of character shaping permits many special character, different sizes of print and to print graphics such as charts and graphs. Dot matrix printers will become auxiliary devices while the laser printers are flooding - in for rough working and extending the useful lifetime of primary printers.
Line Printers
They are impact printers used with most medium and large computer systems for producing high volume paper output. Speed of printing varies from 300 to 2,500 lines per minute. The line length can be either 120 characters or 144 characters. Drum and chain printers are the widely used line printers.
Inkjet Printers
These are nonimpact character printers based on a relatively new technology. They print characters by spraying small drops of ink onto paper. Special type of ink having a high iron content is used. Droplets of ink are electrically charged after leaving a nozzle.
The droplets are then guided to the proper position on the paper by electrically charged deflection plates. Some models allow for color printing. These nonimpact printers cannot produce multiple copies of a document.
Page Printers
These are very high speed nonimpact printers which can produce documents at speeds of over 20,000 lines per minute. Electronics, Xerography and lasers have made these high volume systems possible. They employ electro-photographic techniques and cost very high. These are fit for real-time printing applications like desk top publishing (DTP) and professional publishers for automation. The corporate applications, DTP for design preparation and page layouts, the advertising agendas and graphic designers imaging call for CAD/CAM techniques. Personal computers promise the peripheral market today. The lasers accommodate range from 300 dpi to 600 dpi.
LED Printers
The LED print head consists of 2,496 led elements arranged in a line, driver ICs, lens arrays and frame. When the print head receives the image data signals, the LED elements emit light beams. These light beams are focused on the surface of the OPC (organic photoconductive) drum through a lens array. As the drum rotates, a latent electrical image is formed on the drum surface where the led light beam strikes. Next, the toner is deposited on the exposed area of the drum. The paper gets the image from the drum.
After this, the paper is passed through the fuser. In this way the toner is fused into the paper by heat and pressure and finally the printed page pops out. LED technology enables a multi-functional product which has printer, facsimile and copier functions all together with smaller size than the conventional laser printer. For real good quality of color reproduction thermal transfer and dye sublimation is the answer and for an occasional touch of color with text, inkjet is an affordable solution. Printers thus discussed become a sharable resource on a multi user system and spooling is often one of the important device management task of the present day operating systems more of a batch processing nature.
High speed magnetic tape recorders will be much faster than a high-speed printer which is treated as an ON-line medium on well governed process management systems.
Final printing is done on usual line printer which interprets the recorded tape. But today with visual mediums like the video display unit and data stored on files pagewise, the fastest LASER printers are used for quality as well in critical applications involving image processing and desk-top publishing areas.
A teletypewriter TTY is used as a remote terminal connected to a large scale general purpose computer via telephone lines. Two distinct audio frequencies visualize the binary data. An acoustic tone coupler does the translation. This TTY console consists of basic keyboard and a printer output unit. Most modern TTYs use an eight hole punched paper-tape.
Today with the growing trends in personal computers and multitasking systems the keyboard more like a typewriter board has a host of function keys, control characters besides software mode editors in the real realm of interactive user systems. Interactive machines involve varying sets of users. Thus, the users on interactive machines include the end person using the data base, a person managing a package use, programmers on their language shells, to system analysts and controllers restricted and dedicated with console operations for achieving interactive targets with the robot computer. The cathode ray tube terminal has become a popular interacting medium. This is the fastest sitting strength of a computer centre involving the optical terminology. The CRT output display is driven by vertical and horizontal sweep circuits similar to that used in Television set and oscilloscopes.
Scanning is done several 1000 times/second. Thus the CRT terminal allows quick display of a file or record of information’s. This device also provides for buffering to about 2K memory. The transmission of data across devices with CRT are generally represented in bauds. The pixels on the screen also provide a form of optical character recognition for standard inputs to the essential computing requirements of pattern recognition, etc., in the area of digital image processing with efficient algorithms. It is estimated that 30 to 50010 of installation cost today is met in data preparation support mediums, more so essentially in dedicated computer aided graphic devices for varying applications like machine design, civil eng. and information technology areas. Dedicated systems for CAD applications make use of graphic workstations. Thus for an interactive domain the very fast and easy to use graphic devices have gathered momentum on specific areas. The CGA (color graphic display adaptor) and extended graphic~ adaptor (EGAs) have shown flexibility and provides an artistic look for ease of use.
CRT is a glass enclosed rube having phosphor coated screen where the focusing of electron beam takes place for visibility. Raster scans copes up for animation and dynamic data processing, liquid crystal displays and flat screens have low power consumption and higher capabilities. The main graphic devices used include light pens, touch screens, joysticks, Mouse and digitizers. These graphic medium require dedicated software packages or/and software libraries in a language shell for high compute problems and color graphics animation. The discussion of these graphic devices is left to the reader as an exercise.
The graphics applications have been approved by management professionals, design engineers, SQL-based (structured query language) data base systems and computer aided flexible manufacturing systems. Nevertheless the cost factor of graphic workstations are always accountable. Thus, the input output stores playa vital role with today's technological innovations. In order to convey the needs of input output devices to the CPU, two types of channels known as byte multiplexer and block multiplexer channels making use of interrupt driven mechanism and DMA (direct memory access) respectively are often employed in computing systems. For most of the OS shell commands which directly operate on available executable files, are either satisfied or triggered by direct lines (interfaces) for each of the terminal I/O and the Uni BUS (shared) concept is applicable only for virtual memory management systems. Having discussed on I/O units, it is important to realize that all data communicated across the system are digital (binary in nature) in the overall process. But real-time systems are analog types, involving nonelectrical or electrical Signals. Thus, transducers in the context of computers essentially give rise to an electrical signal (current or voltage) which are considered as analog signals derived from the strength and features of the parameters involved. These must be converted to binary form (often referred as digital) suitable for computing processes during their stay with computers. The analog to digital converters and the digital to analog converters are considered to be the two EYES of the system. In the following the digital to analog converters is explained.
In direct ADCs (analog to digital converters), the analogue Signal is directly converted into digital output without any intermediate conversion step, as in the case of successive approximation type. These are characterized by a short conversion time and are used in instrumentation systems like the data logger. The other types will be mentioned while scanning on ADC s. Many direct ADCs use DAC in the feedback path. A1s~ digital outputs of data acquisition systems must be converted to analog voltage to actuate servomotors, potentiometers etc. A DAC produces an output voltage which is proportional to the input digital number.
Generally D/A conversion is achieved by summing weighted currents at the input of an operational amplifier.
Fig. 20 Weighted resistors D/A circuit
As shown in Fig. 20 the passive resistors form the divider network. A 3-bit DAC is depicted. R_L the load is large enough such that it does not load the divider network. In practical applications a 12 bit DAC means the need for a wide range of resistor values. If the most significant bit (2^11) has a resistor of 10^4 ohms, then the least Significant bit would require a value equal to 2^11 x 10^4 ohms.
The accuracy and stability of the DAC is dependent on the absolute accuracy of the resistances used and their ability to track each other with temperature, especially when the range of values required for good resolution is very large. Conversion rate is relatively slow owing to the high input impedances and speed limitations of the voltage switches.
n - 1 * Zi a·
Eanalog = EReference i ~o (21n _ 1) for "n" input bits.
The least Significant bit has a weight of (2n _ 1) .The full scale output voltage achievable is equal to E Reference when all bits are high "1".
For example, for the 3 bit D A C, the maximum O/P
(20+ 21+22)
= E Reference = E Reference (23 - 1)
1
Thus the precise resolution becomes -,,- * E reference volts.
2 -1
High accuracy calls for very accurate resistor values which means high cost. A well controlled accurate reference power supply able to source/sink considerable currents is again needed. Offset in amplifiers must be quite small and response time is mainly determined by the slew rate of the summing amplifier. The switches shall be required to have a low ON resistance. More often, a DAC is an integral part of analog to digital conversion methods.
Fig. 21 DAC Block Diagram
Fig. 22 gives the circuit for a practical 4 bit 0 to A binary ladder constructed using only two resistance values R and 2R. Here the output voltage is a properly weighted sum of the input bits.
Fig. 22 4-bit binary ladder
From the Venin's theorem, the total resistance looking from any node back toward the terminating resistor or out toward the digital input is 2R. This is true regardless of whether the digital inputs are at ground or E Reference, because the internal impedance of an ideal voltage source is 0 ohm.
The contribution from the different bits are 1/2 for the most significant bit (MSB), ½^2 = 1/4 for the second MSB, ...... so on and 1/2n for the nth bit, i.e., the LSB (least significant bit). Thus the minimum measurable signal is 1/2n times E Reference for n input bits on a practical DAC. The maximum measurement value is 0/2, 1/4, 1/8, 1/16)
2"-1 8 + 4 + 2 + 1 15
'--*E =-"E
2 n "Reference ' 16 16 Reference
...where n is the number of bits reflecting the resolution. So we can say better the resolution, accurate the calibration. A high performance linear operational amplifier can be employed to tap good analog outputs. Fig. 23 gives the practical circuit of a 4 bit DAC.
Fig. 23 Circuit of 4 bit DAC
The level amplifiers work in such a way that when the flip-flop status is High, the amplifier output is EReference = + 10 volts, otherwise 0 volt. The R value can be conveniently chosen between 5KOhm to 50 KOhm which lends to manufacture by thin-film deposition techniques that improve the temperature tracking capabilities; thin film nickel chromium R-2R ladder networks, featuring tracking with temperature to better than 1 part per million/DC are commercially available.
The DAC is used at the output of the computer and if the application pertains to a process control system involving many parameters, the signal output must be held between sampling periods using sample and hold amplifiers as in Fig. 24.
Fig. 24 Sample and hold amplifier
The sampling theorem is used in practice to determine minimum sampling speeds. If the sampling rate in a system exceeds twice the maximum signal frequency, the original signal can be reconstructed at the destination with vanishingly small distortion without any sampling errors.
As in figure 24, when the switch is closed, the capacitor charges to the DAC output voltage. When the switch is opened, the capacitor holds the voltage level until the next sampling period. The operational amplifier provides a large input impedance so as not to discharge the capacitor appreciably and at the same time offers gain to drive external circuits.
Linearity or relative accuracy is the maximum deviation of the output compared with the desired output. The speed of DAC refers to the time necessary for analog output to settle down within desired accuracy. Resolution defines the smallest increments in signals that can be discerned.
Fig. 25 gives DAC with a current output. Binary -Weighted current-; are generated using active sources and the output is obtained by summing them on a common output bus.
Fig. 25 DAC with a current output
The errors involved in this type of conversion usually limits its accuracy to about 12 bits. A full scale output current of 10 mA is ideal, since a 1 volt output would develop across a load resistance of 100 ohm, an approximate impedance level for high-speed coaxial cable operation. Multiplier type DAC is one which is specially designed to accept a varying reference voltage.
The output magnitude is directly proportional to the product of the reference voltage and the digital input. The reference can be a bipolar or AC source and its performance depends mainly on the type of electronic switches used. For example, FET switches are most suitable for the bipolar reference mode.
MDACs are extensively used in programmable test equipments where the amplitude of a varying or OC signal can be controlled by a digital computer. They are also used for graphic displays since they can perform direct multiplications such as R sin theta which is required for conversion of polar to rectangular coordinates in microseconds.
DACs in Integrated form are used in peak detectors, voltmeters, stepper motor drive and programmable systems.
Analog to digital conversion (ADC)
In indirect ADCs, an analog signal is converted into an intermediate form which is driven to digital output. The dual slope converter is one of integrating type.
The analog input is converted to a proportional time interval known as voltage to time conversion. Then by counting, the digital output is achieved which offer inherently high accuracy with simple circuitry. These are slower and very commonly used in digital instrument like digital voltmeters.
Direct ADCs are characterized by a short conversion time finding applications in real-time instrumentation and process controls. The various methods of direct ADCs include simultaneous or parallel conversion, counter ramp type, successive approximation method, servo and delta modulation ADC. The process of approximating the input value is called quantizing.
In analog to digital conversions, resolution is quantified as the change in analog input voltage for obtaining a 1 bit (1sb) change in output.
Resolution = - E /2 n -1 -- where E is maximum swing in input and “n" is the number of output bits. Drift refers to the change in the output for the circuit parameters with time and temperature. Very low drift is achieved at high cost and complexity. The speed of AID converter is measured by the time to perform one conversion or the time between successive conversions at the highest possible rate. Some of the advantages achieved for digital display of measured data in instrumentation systems are;- allows practically unlimited precision; offers very slow ageing rate; noise effect on system accuracy can be reduced considerably.
Analog techniques are preferable in certain applications wherein a peak or null has to be obtained (setpoints) and small variations in certain parameters are to be recorded or displayed continuously (for example, the speedometer of a moving vehicle on road). The simultaneous ADC is shown in Fig. 26.
Fig. 26 Simultaneous ADC
This is the fastest method. The reference voltage to each comparator is fed using a precise voltage source and potential divider network. The input Eanalog is fed to another input line of the op. amp. comparators. Thus the circuit shown provides only a 2 bit output with 3 comparators. In general, an n-bit output requires (2n - 1) comparator units which is costly but finds application in supercomputers, real-time ON-line adaptive control systems, space research and simulation domains.
Nevertheless the more general types of ADC are the counter-ramp and simultaneous approximation procedures. Fig. 27(a) gives the counter type of analog to digital converter.
Fig. 27 (a) Counter-ramp type A to D
Fig. 27 (b) Control logic of Fig. 27 (a)
The variable reference is achieved by a counter and DAC arrangement which is continuously scanned by the comparator with E analog and the output is displayed when the conversion is over on digits. The control logic is shown in Fig. 27 (b) which employs a flipflop and a monostable control to stop the counter at the appropriate instant. The speed of ADC is governed by the clock period and also the counter size. Continuous AI o requires the use of an up/down counter and additional control.
Example: Calculate the assured maximum conversion rate of the ADC if the output is 8 bits and the clock frequency is 500 KHZ. The number of counts = 2^8 = 256.
Time for 1 count = 3 = 2 uS. 500 x 10
Time for 256 counts = 512 s.
The average conversion time = 512/2 -= 256uS
Assured maximum Speed =1/512 * 10 ^-3 = 1953 conversions/second.
Successive approximation method
This involves the process of approximating the analog voltage by trying one bit at a time beginning with the most Significant bit. This is a relatively optimum approach giving fast conversions with critical design of circuits. Also more of the practical ADC chips employ the successive approximation type especially with microprocessor based systems. Speeds as high as 100 ns/bit can be achieved. The accuracy depends on the stability of the E reference, the level converters, the D to A network and the comparator. Fig. 28 gives the block schematic of this method of ADC.
To start with, a "start conversion pulse" clears the output register and turns ON its msb so that the 0 A C gives half of a full-scale deflection. This output IS compared with the analogue signal, and if E analog < DAC reading, comparator turns off the msb of the output register via the control logic unit. And if E analog > DAC, the msb in output register is left ON. The next clock pulse turns ON the next significant bit in the output register via the shift register. The process is repeated n times for an bit converter until the 1sb has been compared. Then the clock stops, to be restarted only by the next "start conversion pulse".
Fig. 28 Block schematic of ADC.
The "status" line changes state to indicate the contents of the output register now constitute a valid conversion. The analog input must not change during the conversion interval and if it does, a sample-Hold device is used to hold the input signal value constant during the conversion interval and the "status" Signal is used to release the "HOLD" mode to again sample at the end of conversion. Assuming a 10 bit converter and a 1 MHz clock, the conversion time for 1 sample = 10 x 10^6 S = 10 uS. Differential linearity is a measure of A to D converter performance which reflects the variation in voltage-step size which causes the converter to change from one state to the next and is usually expressed as a percent of the average step size.
The counter and continuous type ADCs possess better differential linearity than successive approximation type. Up-down counters are employed in continuous conversion systems offering better speeds. In isolated analog control instrumentation, the indirect ADCs using voltage to time conversion technique are often used for real-time robots.
In pulse and digital circuitry, the high impurity p-n junction devices like tunnel diodes made of germanium or gallium arsenide are used. Ga As provides a high Iu/lv ratio (Peak to valley current). For computers, devices with Ip in the range of 1 to 100 mA are common. Tunnel diode offers high speed, low noise, low power and environmental immunity.
Opto electronic devices
In a photodiode, reverse-biased p-n junction is illuminated and the current varies linearly with the light flux. It is the fastest photo detector coping with nS switching rates.
The reverse current is in the order of uA for photodiodes. Photo transistors are applicable for real computing where the switching time is of the order of uS and the output current mA range.
Solar cell is unbiased because it is used as an energy source. It is physically larger and is more heavily doped than a photodiode.
LED
The energy released when an electron falls from the conduction into the valence band appears in the form of infrared radiation. The o/p light power increases with injected current input. Light emitting diodes give off light when forward - biased. GaAs for infrared radiation, GaAsP for red or yellow light and GaP for red or green light is the nomenclature of usage. Red has a wave frequency of 4 (10^14 ) Hz, green 6(10^14) Hz whereas blue has 8(10^14)Hz.
Photon energy E = h f, where h= planck's constant = (6.63 • 10^-34)
E = energy in joules; f = frequency in Hz.
Color of radiation depends on frequency and brightness on number of photons received/second.
LEDs are used in display systems and they do (led arrays) supply input power to LASERs or entering information into optical memories. Lasers are seldom used in advanced color televisions and holograms for 3-D imaging.
5. FUTURISTIC MEMORY TECHNIQUES
In the use of electronic memory, the octal buffers/drivers with tristate outputs improve the performance figures of serial transceivers also increasing the density of printed circuit board in interfacing area. Quadraple bus transceivers for asynchronous two way communication between data buses with propagation delay just of the order of 14 to 24 ns is already available in market with full TTL., and CMOS compatibility. CMOS ROMs from 16K to 64K bytes organized in 8 banks already assist in memory interleaving on time shared machine with access times of 350 to 450 nS. FAST logics have become important in microprocessor systems. The fabrication components to support the devices area is detailed below: FAST is a trademark of Fairchild Camera and instrument Corporation.
The small geometries associated with oxide-isolation makes complex functions possible with very high-speed and low power characteristics. The speed of devices are fixed primarily by the node capacitance of the device junctions. Using the smallest practical resistor size creates the current Schottky family of high-speed logic. Input loading and short-circuit protection are the major difficulties in implementing high-speed circuits.
Thus mainly in critical areas like super -computing, Schottky TTL has found an impact besides the usual emitter-coupled logic. They operate on FT, up to a few GHZ. The importance of using high-speed bipolar circuits in conjunction with relatively slow MOS memories has called for SEC-DED codes Hardware.
They generate 6- bit and 7-bit check-words from 16 or 32 bit words. Each check word is stored along with a corresponding dataword, during the memory write cycle.
During the memory READ cycle, the 22 or 39 bit word retrieved is analyzed and SEC DED facility is achieved as well the gross-error condition (all 1's or 0's) of unidirectional errors is detected.
The input capacitance of 256 K NMOS DRAM is of the order of 8 pF. The maximum size of the memory that can be driven by one controller is set by the maximum output capacitance that can be safely driven by any output - 256pF. This dictates the effective fanout of the controller to 32 and the maximum memory size to 1 M byte. The oxide-isolated fast TTL has addressed octal functions for buffers & transceivers, error control and dual bus data transfers in high- performance microprocessors.
Multiport memories are also called shared memories by more processors. The most common configuration is the dual-port memory with 2 processors sharing the same array.
Applications range from Simple message passing between processors in a loosely-coupled environment to multiple processors executing from a common program memory in tightly - coupled systems. (e.g. with CRT controllers of shared memory). The display memory must be accessed by the controller to refresh the display and by the microprocessor to update and manipulate data on the screen.
Static RAMs are preferred over dynamic RAMs because the latter require refresh circuitry which adds another port to the array, and also decrease maximum throughput rates in fast systems. The dynamic RAMs offer reduced power consumption and large storage capacity in a single memory chip. Optical memories employ a 64 kilobytes dynamic RAM for image processing which possesses enough resolution to be applied to robots (ultrasonic vision up to 10 meters). Dynamic microprogramming calls for occasional writable control stores. More often multi-port memories are small in Size (density). The multiport memories include the control logic for the status of use to the users, may be, besides providing priority.
A micron Eye camera employing an OPTIC RAM (64 kilobits of dynamic RAM) has been developed by micron technology. It contains a printed circuit board with suitable interfacing circuitry so that it can be interfaced to a microcomputer. With this type of sensors, bit pattern of images are stored in the computer memory. It has enough resolution to be applied to robots, as in ultrasonic vision accommodating up to 10 meters with a resolution of 3mm.
Optical Systems
The optical system where the input and output are essentially 2-D spatial patterns are immune to electromagnetic interference, a desirable feature in optical interconnections.
liquid crystal light Valve (LCLV) act as optical storage cells equivalent to electronic primary memory; whereas high density secondary memory being implemented by optical disks ' and holographic stores.
Table 4 Summarizes some factors of optical storage systems.
Optical reading of the magnetically stored data is based on the Faraday effect. Optical writing of magnetic information involves thermomagnetic effects. Erasable magneto-optic disks are now at advanced stages of development. The holographic memory for read only on-line data processing, the hologram is reconstructed for electronic processing. From literature, the optical memories are susceptible to only unidirectional errors which gives an edge of reliable computing over the electronic counterparts. It is fairly easier to construct codes for information reliability for this kind of errors with lesser redundancy. Fiberoptics are already in use in Local area networks (to connect computers to peripherals) providing a noise-free communication. Optical computers promise to the area of SIMI) machine of processing 2-D images, biomedical image processing being a typical candidate. It can be hoped in future, the new technology of optical computing may meet the pattern recognition and neural computing ends in a narrow origin.
The performance figures of any type of memory can be realized only by a detailed study of how much storage and how long the same is used in discrete or continuous modes. This also leads to problems in virtual memory management for good process designs. Memory interleaving in Hardware amounts to account for reliability in systems which can be further brushed up by using error control mechanisms. Magnetic bubbles and charge-coupled devices promise to be the stores for bit slice architectures. The holograph memories serve as data storage for bulk data with light technology in Image processing. Already the optical memories serve well as offline banks for pattern recognition and data communications. Optical memories are more susceptible to unidirectional class of errors better suited for reliable computing area.
6. MEMORY BASED ARCHITECTURES
The stack addressing machines have very little complexity for access coding and applied in a narrow range of problems like single language domain, process control of machine tools, etc with reprogrammable features. The various methods of main memory access will decide the processor architectures. The memory organizations of interleaving and bit slice process lend themselves for sensitive data processing domains. The paging and memory segmentation of virtual systems attract many users converging on MIMD and SIMD benches creating the cohesion and security problems. On-line productive environments altogether call for graphics and device usage in all engineering integrated manufacturing. Beyond all, the super-computers have to address still the associative memory concepts, cache hits, multi-bus protocol dataflow and pipelining. In conclusion, the memory must be construed not as empty set but as an intelligent informative tool for real file maintenance in a broad base of applications.
TERMS
Algorithm, microcontroller; Electron, electron-volt. semiconductor. Doping, cut-in voltage, Kirchhoff; Register, byte, Word organization, 3-D organization. Cryogenic, throughput, random access, Astable, monostable, flipflop. flag, decoder, random access memory, memory-mapped I/O, dynamic memory, RISC, EPROM, Cache, Hit ratio, Perform, Merge, PLA, arithmetic; Turn-around-time, EBCDIC, NRZ, VIRUS; printers, primary output, non-Impact printers, spooling, Laser printer, teletypewriter, graphic, DMA, resolution, Quantization, Counter, tunnel diode, light emitting diode, Optic RAM, LCLV, Reliability, Unidirectional, dataflow.
QUIZ
1. Define wordlength of central processor.
2. Correlate the machine language to the constituents of a CPU.
3. What is stored program execution?
4. Quantify an instruction cycle.
5. Why should unconditional jump instructions be avoided in preparing program inputs?
6. Mention the various types of semiconductor memory technologies and bring out the characteristics of each.
7. What are the major points taken into consideration while selecting the CMOS chips?
8. Define the terms Fan-out, and noise immunity of a logic gate. What is emitter coupled logic?
9. Sketch the organization of registers in Intel 8085. What is the advantage of pairing registers?
10. .Compare register and stack addressing modes. Distinguish between clock, machine and instruction cycles. With timing diagram explain the fetch cycle for 8085.
11. Define THRUPUT of yourself as a programmer.
12. What is the significance of E format in Fortran language for floating point arithmetic in system optimizations?
13. How do Cache memories help in improving program runtimes?
14. How many address pins are required to access 4K memory locations?
15. How do the flags help a microprocessor for program data flow and for self-testing towards reflecting the abilities of a computer?
16. Mention the merits of hexadecimal code in minimal microprocessor systems.
17. How is a programmable I/O port superior to a simple 8212 I/O latch?
18. How a processor status word differ from the program status word on a UNIX bench?
19. Mention the merits of crystal oscillator usage for microprocessor clocks.
20. Explain the purpose of various segment registers of 8086 microprocessor.
21. (a) When is the need for dynamic electronic memories? (b) Give example of anyone static RAM chip and explain its constructional details and usage.
22. Explain anyone procedure for internal sorting.
23. Comment on the register storage requirement of floating point arithmetic activity.
24. Attach a note on D flipflops for buffering.
25. When are EPROM s desirable in micro computer development systems?
26. A digital computer has a memory unit at 8192 words, 36 bits/word. The instruction code format consists of 5 bits for operation code and 13 bits for address part. Two instructions are packed in one memory word and a 36 bit instruction register is available in control unit. Formulate the FETCH and EXECUTE cycles for the computer.
27. What are the different types of mapping procedures in the organization of Cache memory? Explain in detail.
28. Mention the specialty of stack segments at execute time and correlate the same with Cache usage.
29. Correlate the terms accuracy and range of numbers in the exponent mantissa format for enhancing the architectural capabilities of machines.
30. Express the effective address for the following schemes. Direct, Indirect and pre indexed indirect.
31. Give the differences between virtual memory and Cache memory and discuss the implementation of associative memory.
32. Explain DRAM refreshing. How is refreshing done?
33. With a neat sketch explain the basic working of a memory chip.
34. Compare the features and characteristics of PROM and EPROM.
35. What is absolute addressing? Write an exhaustive note on immediate addressing mode.
36. The access time of a Cache is 10 ns and that of main memory is 1000 ns. It is estimated that 80010 of the memory requests are for read and the remaining 20010 for write. The hit ratio for read accesses only is 0.9. A write-through procedure is used.
(i) What is the average access time of the system considering only memory read cycles? (ii) What is the average access time of the system for both read and write requests? (iii) What is the hit ratio taking into consideration the write cycles?
37. Explain the techniques used to avoid racing in sequential circuits.
38. Define the roles played by the program counter and flag status registers of a central processing unit.
39. A 2-D RAM has N addressable locations. Show that the number of address drivers is minimum if and only if the memory is organized as a square matrix.
40. The address of a terminal connected to a data communication processor consists of two letters of the alphabet or a letter followed by one of the 10 numerals. How many different addresses can be formulated.
41. How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes? How many lines of the address bus must be used to access 4096 bytes of memory?
42. Differentiate bit and byte organized memories for systems reliability.
43. Write clear notes on the capabilities of JK flipflops in memory design.
44. What is cache miss rate and how is it helpful on intelligent search applications.
45. Write a note on resolution of monitors as I/O support.
46. Describe anyone Output device suitable for use with a mainframe computer.
47. Describe anyone memory management scheme with suitable block diagram for a modem computer system.
48. Mention the applications of clippers and dampers in pulse control circuits.
49. A ROM has the following timing parameters:
Maximum address to valid data output delay= 30 nsec.
Maximum chip select to valid data output delay= 20 nsec.
Minimum Data Hold time (After address change or after chip deselect) = 10 nsec
Assume that, the chip is selected using one of the address lines, and, the data set up time is negligible.
What is the maximum rate at which a CPU can continuously read data from this ROM? (show your calculations step-by-step)
50. In a two-level virtual memory, the memory access time for main memory t_A1 = 10^-8 sec, and the memory access time for the secondary memory. T_A2 = 10^-3 sec. What must be the hit ratio, H such that the access efficiency is within 80 percent of its maximum value?
51. (a) For the synchronous counter shown in figure below, write the truth table of Q0, Q1 and Q2 after each pulse, starting from Q0 = Q1 = Q2 = 0_1, and determine the counting sequence and also the modulus of the counter.
(b) Design a 3-bit counter using D-flipflops such that not more than one flipflop changes state between any two consecutive states.
52. A microprocessor is capable of addressing 1 megabyte of memory with a 20-bit address bus. The system to be designed requires 256 K bytes of RAM, 256 K bytes of EPROM, 16 I/O devices (memory mapped VO) and 1 K byte of EERAM (electrically erasable RAM). (a) Design a memory map (to reduce decoding logic) and show the decoding logic if the components available are: Type Size Speed RAM 64Kx8 140n sec EPROM 256Kx8 150n sec EERAM 256x8 500 n sec - read, 3m sec -write.
(b) The microprocessor is operating at 12.5 MHZ and provides time equivalent to two clock cycles for memory read and write. Assuming control signals similar to 8085, design the extra logic required for interfacing EERAM.
53. When is it desirable to store programs and data in separate memories on a time shared multiuser system?
54. Discuss how the speed compatibility between a central processor and a memory device is ascertained.
55. Explain the need for auxiliary memory devices. How are they different from main memory and from other peripheral devices?
56. A certain moving arm disk - storage device has the following specifications: number of tracks per surface = 404, track storage capacity = 13030 bytes, disk speed = 3600 rpm, Average seek time = 30 m secs. Estimate the average latency, the disk storage capacity and the data transfer rate.
57. Explain the terms seek time and latency with serial access stores.
58. Compare Assemblers with compilers towards speedup in generating obj. code.
59. Elaborate the distinct differences of an encoder from a multiplexer.
60. What are the uses of a demultiplexer? 61. What is binary search of an organized me and what is the time complexity for retrieval? 62. Writ~ a note on the usefulness of user stacks to good operating systems.
63. What is racing in sequential processes and exhaust on the methods to arrest the same.
64. Can a disk be used with bad sectors? If so, how and how long? If not, how is the disk replacement carried out? 65. Mention some essential and desirable hints for portability and portability respectively of floppy disks.
66. Why is databus bidirectional?
67. Distinguish a floating BUS from a fetched BUS for a UNIBUS architecture.
68. Mention few applications of priority encoder in interrupt driven I/O for communications.
69. What is the purpose of monitor ROM with reference to minimal I/O in microprocessor systems?
70. Give a clear Cost/Trade analysis supporting packages in the ASICs area for end users.
71. Bring out the superior measures for light emitting diodes in display systems compared to the seven-segment displays.
72. What is lexicographic sort and how are alpha-numerics compared in a character set?
73. Mention a few distinct advantage of a CPU incorporating the serial communication facility in addition to the usual bus strategy with I/O systems architecture.
74. Assuming a 8 bit DAC, compute the resolution of a binary ladder with + 10 volts treated as "HIGH" and 0 volt as "LOW" logic levels.
75. Explain crisply the easiness of 'e' language for graphic displays. Also remark how color can act as a third dimension for computer vision?
76. What do you understand by I/O processor?
77. Bring out the differences between isolated I/O and memory-mapped I/O.
78. Describe the analog to digital conversion technique employed in a digital voltmeter.
79. Compare the two basic types of D/ A converters using resistors.
80. An ADC which will encode pressure data is required. The input signal is 666.6 mv/psi. If a resolution of 0.5 psi is required, find the number of bits in the A to D converter. The reference is 10 volts. Also find the maximum measurable pressure.
81. What are the disadvantages in software simulation of analog to digital conversions for analog input readings?
82. Explain the operation of a Schmitt trigger circuit for pulsing activity in digital systems. Define duty cycle of astable multivibrator.
83. How are analog to digital conversion methods evaluated? Explain anyone ADC technique.
84. Write a note on multiplier type DACs.
85. How are utility programs different from systems programs and also how they influence the software objectives?
86. Write a well detailed note on modularization criterion for structured programming methodology.
87. Explain the direct memory access for distributed processing in loosely coupled networks. Also comment on CMOS suitability for high speed computers.
88. State a few specific examples involving arithmetic inviting the use of loop-up tables.
89. Explain the operations on queue and stack data structures.
90. What is a DEqueue structure and contrast the same with exchange instruction.
91. What are the advantages delivered by using bit/memory chip organization?
92. Clearly distinguish memory-mapped 110 from I/O - mapped I/O architectures.
93. What are the desirable features in addressability for a multiuser system with identical I/O units? Also highlight on the interrupt driven transfers for this interactive environment.
94. What is the purpose of password concept on multi programmer domains? Highlight the same with the idea of secure systems.
95. Bring out the need for subroutines and Macros.
96. How are function subprograms decided to be included in computing systems? How are they consumed on a multiuser system?
97. If a system has two stack pointers, comment on the use of one stack exclusively for the user as a bonus in computer organizations.
98. Why computer architects provide upward compatibility in their products? What is simulation in the realm of revolving architectures?
99. Write notes on (a) arithmetic pipelining in the case of scarcity of compute dements as in RISC machines and (b) for representing numeric data with CPU in-storage scarcity.
100. Comment on instruction complexity biased with respect to instruction lengths.
101. Mention the specialty of JK flipflops in up/down counting for CPU delays in reconfigurable systems as a test measure.
102. Write dear notes on arithmetic algorithms for computations beyond the capability of a machine. Highlight ( spell out) your approach in simple words with specific examples.
103. Mention the objectives of VLSI testing for digital semiconductor memories.
104. Why should there be separate address and data buses? Mention their merits on memory shared architectures.
105. What was the basic feature of the UNIX operating system from the eyes of Language designers?
106. What is the need for computing – algorithms.
107. What is segmentation? Compare it with paging. What is page-fault?
108. What do you mean by stack-based machine architecture?
109. Explain the technique of designing parallel memories for loosely and tightly coupled systems.
110. What are the databases and data structures used in each phase of compilation?
111. Write notes on storage allocation in FORTRAN, with special reference to COMMON and EQUIVALENCE declarations.
112. Write a note on Amdahl effect.
113. Explain anyone DOS and UNIX shell commands as an on-line user.
114. Write a detailed note on CMOS-TTL interfacing for digital systems.
115. Compare the activities following an hardware interrupt from that of a software interruption.
116. What are the specific advantages of memory segmentation along with cache memory in application domains?
117. A queue Q containing n items and an empty stack S are given. It is required to transfer all the items from the queue to the stack, so that the items at the front of the queue is on the top of the stack, and the order of all the other items is preserved.
Show how this can be done in 0 ( n) time using only a constant amount of additional storage. Note that the only operations which can be performed on the queue and stack are Delete, Insert, push and pop. Do not assume any implementation of the queue or stack.
118. Clearly outline the structural organization towards memory optimization in a distributed data processing COBOL interactive environment towards computerization.
119. Write clear notes on photodiode and Light emitting diodes.
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