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1. Introduction
Earlier sections explain the concepts and terminology that are essential to an understanding of computer architecture. The sections discuss the fundamental aspects of processors, memory, and I/O, and explain the role of each. Previous sections discuss how parallelism and pipelining are used to improve performance.
This section considers a few architecture examples. Instead of introducing new ideas, the section shows how the ideas in previous sections can be used to describe and explain various aspects of digital systems. The examples have been chosen to show a range of possibilities.
2. Architectural Levels
Recall from earlier sections that architecture can be presented at multiple levels of abstraction. To help us appreciate how broadly architectural concepts apply to digital systems, we will explore a hierarchy of architectural specifications. The hierarchy ranges in size from a complete computer system to a small functional unit on a single integrated circuit. We use the terms system-level architecture (sometimes called macroscopic architecture), board-level architecture, and chip-level architecture (some times called microscopic architecture) to characterize the range. For each level, we will see that the concepts from earlier sections allow us to understand both the basic components and their interconnection. Furthermore, we will see that at a given level, it is possible to specify a logical (i.e., conceptual) architecture or to specify a more detailed implementation. FIG. 1 summarizes the levels we will consider.
Level | Description
System -- A complete computer with processor(s), memory, and I /O devices. A typical system architecture describes the interconnection of components with buses.
Board -- An individual circuit board that forms part of a computer system. A typical board architecture describes the interconnection of chips and the interface to a bus.
Chip -- An individual integrated circuit that is used on a circuit board. A typical chip architecture describes the interconnection of functional units and gates.
FIG. 1 Conceptual levels of architecture and the purpose of each.
3. System-level Architecture: A Personal Computer
Conceptually, a personal computer consists of a processor, memory, and a set of I/O devices that all attach to a single bus. In practice, however, even a personal computer contains a complex assortment of buses and interconnection mechanisms that are each designed to fill a specific role.
Some of the variety and complexity in underlying hardware arises from special performance requirements and cost. For example, a video card needs much higher data throughput than a floppy disk, and a high-resolution screen requires more throughput than a low-resolution screen. Unfortunately, the hardware that interconnects a device to a high-speed bus costs significantly more than the hardware that interconnects a device to a low-speed bus, which means that using multiple buses can lower the overall cost of the system.
A second motivation for multiple I/O buses arises from a vendor's desire to pro vide a low-cost migration path to newer, more powerful systems. That is, a vendor strives to create a processor that offers the advantages of higher performance and more capabilities, while simultaneously retaining the ability to use existing peripheral devices.
We use the term backward compatibility to characterize the ability to use existing pieces of hardware.
Backward compatibility is especially important for bus architectures because a bus forms the interconnection between an I/O device and a processor. How can a computer vendor devise a new, higher-speed bus while still retaining the ability to attach older peripheral devices? One possibility consists of creating a processor with multiple bus interfaces. A much less expensive answer lies in the use of bridging.
4. Bus Interconnection and Bridging
The use of bridging for backward compatibility is easy to understand through a historical example. At one point in history, all personal computers used an Industry Standard Architecture (ISA) bus that was developed by IBM Corporation. Peripheral devices for PCs were designed with an interface for the ISA bus. Later, a higher-speed bus architecture was developed: a Peripheral Component Interconnect (PCI) bus. The two standards for PC buses are incompatible -- an interface that plugs into an ISA bus cannot be connected to a PCI bus. Thus, if a user owns ISA devices, the user is less likely to purchase a computer that only accepts PCI devices.
To entice computer owners to upgrade their computers to a computer with a PCI bus, vendors created a bridge to interconnect the new PCI bus and the older ISA bus.
Logically, the bridge provides the interconnection that FIG. 2 illustrates.
FIG. 2 Conceptual view of a PC architecture that uses a bridge to inter
connect an ISA bus and a PCI bus. The bridge makes it possible to use older
ISA devices with a newer processor.
In the figure, the CPU and any I/O devices that have a PCI interface connect directly to a PCI bus. The bridge provides a connection to an ISA bus that is used by I/O devices that have an ISA interface. In the best case, the interconnection provided by a bridge is transparent. That is, each side uses a local bus protocol to communicate without knowing about the interconnection -- the CPU addresses ISA devices as if they are connected to the PCI bus, and an ISA device responds as if the CPU is connected to the ISA bus.
5. Controller Chips and Physical Architecture
Although the architecture illustrated in FIG. 2 provides a conceptual explanation of a PC architecture, an implementation is much more complex than the figure indicates. First, although a PC provides slots that external devices use to connect to each bus, the PC does not use the same technology internally. Instead, a PC usually contains two special-purpose controller chips that provide all the bus and memory interconnections. Second, controller chips are configured to give the illusion of multiple buses.
To understand the need for controller chips, consider the functionality required in a PC. An architect needs to connect the processor, memory, and I/O bus (or buses). In addition to providing electrically compatible interconnections, the architect must design a mechanism that allows one component to communicate with another. For example, both the CPU and I/O devices need to access memory.
Unfortunately, replicating hardware interfaces is expensive. In particular, an architect cannot afford to build a system in which each component has multiple interface units that each handle communication with one other component. For example, although the processor and most I/O devices need to access memory, the cost prohibits an architect from providing a memory interface for each device.
To save effort and expense, architects often adopt the approach of using a centralized controller chip. A controller chip contains a set of K hardware interfaces, one for each type of hardware, and forwards requests among them. When a hardware unit needs to access another hardware unit, the request always goes to the controller. The controller translates each incoming request into the appropriate form, and then forwards the request to the destination hardware unit. Similarly, the controller translates each re ply.
The key idea is:
Architects use a controller chip to provide interconnection among components in a computer because doing so is less expensive than equipping each unit with a set of interfaces or building a set of discrete bridges to interconnect buses.
6. Virtual Buses
A controller chip introduces an interesting possibility. Because a bus is used to communicate, we expect two or more devices to be attached to each bus (e.g., a processor and a disk). In a computer that uses a controller chip, however, it is reasonable to create a bus that contains exactly one connected device. For example, if only one de vice needs an ISA bus and all others use a PCI bus, a controller chip can be created that uses the ISA protocol to communicate with the ISA device and uses the PCI protocol to communicate with other devices. Even if the controller chip uses the ISA protocol to communicate with the ISA device, the computer will not need slots for ISA devices and will not have a physical ISA bus in the usual sense. That is:
A controller chip can provide the illusion of a bus over a direct connection; there is no need for the physical sockets and wiring that is normally used with a bus.
The concept of a controller chip that can provide the illusion of a bus over a direct connection allows architects to generalize the notion of a bus. Instead of separate physical entities with parallel wires, a silicon chip can be used to create the appearance of a bus. We use the term virtual bus to describe the technology. For example, a controller can be created that presents the illusion of one virtual bus per attached device. As an alternative, a controller can be created that combines one or more virtual buses with connections to one or more physical buses. Later sections show examples.
Typically, PC architectures use two controller chips instead of one. The controllers are known informally as the Northbridge and Southbridge chips; the Northbridge is sometimes called a system controller. The Northbridge connects high-speed components, such as the CPU, memories, streaming communications controllers, and an Advanced Graphics Port (AGP) interface that is used to operate a high-speed graphics display. The Southbridge, which attaches to the Northbridge, provides connectivity for lower-speed components, such as a PCI bus, a Wi-Fi network interface†, an audio de vice, keyboard, mouse, and similar devices. FIG. 3 illustrates the physical inter connections in a PC architecture that uses two controller chips.
As the figure shows, a controller chip must accommodate heterogeneity because a controller can connect to multiple bus technologies. In the figure, for example, the Southbridge provides connections for a PCI bus, a USB bus, and an ISA bus. Of course, the controller must follow the rules for each bus. That is, the controller must adhere to the electrical specifications, ensure that all addresses lie within the bus ad dress space, and obey the protocol that defines how devices access and use the bus.
Vendors who manufacture CPUs usually offer a set of controller chips that are designed to interconnect a CPU with standard buses. For example, Intel Corporation offers an 82865PE chip that provides the functionality of a Northbridge and an ICH5 chip that provides the functionality of a Southbridge. More important, the Intel processor chip and Intel controller chips are designed to work together: each chip contains an interface that allows the chips to be directly interconnected, and each chip performs the translation necessary to connect heterogeneous devices.
†Networks that operate at gigabit speeds connect to the Northbridge.
FIG. 3 Example of a system-level architecture that shows the physical
interconnections in a PC that uses two controller chips. Components that require
the highest speeds attach to the Northbridge controller.
7. Connection Speeds
The connections illustrated in FIG. 3 typically use a parallel hardware inter face that has a fixed width and is engineered to operate at a fixed clock rate to deliver a specified throughput. FIG. 4 lists typical values for the clock rate, width, and throughput of major connections.
FIG. 4 Example clock rates, data widths, and throughput for connections
in the architecture that FIG. 3 illustrates.
For comparison purposes, the figure includes the FCC's definition of an Internet connection (25 megabits per second downstream, which is 3.1 megabytes per second) and a register file in a modern processor. Note that transfers in a computer can occur much faster than a broadband Internet connection, and the sustained throughput to registers dwarfs all other throughputs listed in the figure.
8. Bridging Functionality and Virtual Buses
As the names Northbridge and Southbridge imply, the two controllers provide bridging functionality. For example, the Northbridge chip bridges memory, high-speed devices, and the Southbridge chip. The Northbridge presents the CPU with a single, unified address space that includes all of the above. Similarly, the Southbridge com bines the PCI bus, ISA bus, and USB bus into a single, unified address space, which be comes part of the address space that the Northbridge presents to the processor.
Interestingly, a set of controllers does not need to bridge all devices into a single address space. Instead, the controller can present the CPU with the illusion of multiple virtual buses. For example, a controller might allow the CPU to access two separate PCI buses: bus number zero contains the CPU and memory, while bus number one contains I/O devices. As an alternative, a controller might present the illusion of three virtual buses: one that contains the CPU and memory, another that contains a high-speed graphics device, and a third that corresponds to the external PCI slots for arbitrary de vices. Although it is not particularly interesting to a programmer, the separation is crucial to a hardware designer interested in performance because the controller chip can contain parallel circuitry that allows all virtual buses to operate at the same time.
9. Board-level Architecture
The architecture in FIG. 3 includes a Wi-Fi interface as one of the units in a personal computer. The role of the interface is straightforward: provide the physical connection between the PC and the Wi-Fi radio, and transfer data that the PC sends over the network as well as data that arrives over the network. Physically, a Wi-Fi interface can be integrated onto the motherboard in a laptop or reside on a circuit board in a desktop system. In either case, the logical interconnection remains the same.
A network interface card contains a surprising amount of computational power. In particular, an interface usually contains an embedded processor, instructions in ROM, a buffer memory, an external host interface (e.g., a PCI bus interface), and a connection to the radio transmitter and receiver. Some interface cards use a conventional RISC processor; others use a specialized network processor that is optimized for handling net work packets. FIG. 5 illustrates a possible architecture for a LAN interface that uses a network processor.
FIG. 5 Example architecture of a network interface card used for a Wi
Fi device.
Why might a Wi-Fi interface need two types of memory? The primary motivation is cost: although it is faster, SRAM costs more than SDRAM. Thus, a large SDRAM can be used to hold packets, and a small SRAM can be used for values that must be accessed or updated frequently (e.g., instructions for the network processor to execute). In this particular example, the two memory connections are chosen because the network processor described in the next section uses both SRAM and SDRAM.
10. Chip-level Architecture
We said that a chip-level architecture describes the internal structure of a single integrated circuit. As an example, consider the network processor in the board-level architecture illustrated in FIG. 5; the figure uses a rectangle to depict a network processor. If we move to a chip-level architecture, we can examine the internal structure of the chip. FIG. 6 shows the chip-level architecture of a Netronome network processor.
FIG. 6 Example of a chip-level architecture that shows the major internal
components of a Netronome network processor. Access units provide connections
outside the chip.
Intel Corporation designed the network processor, and later sold the design to Netronome.
It is important to remember that the entire figure refers to a single integrated circuit. As the figure shows, the network processor chip contains many items, including various external interfaces, an onboard scratch memory that provides high-speed storage, and multiple, independent processors. In particular, the chip contains a set of programmable RISC processors, known as microengines, that operate in parallel as well as an XScale RISC processor. The XScale provides a general-purpose processor that manages other processors and provides a management interface. When the network processor operates, the XScale runs a conventional operating system, such as Linux. To indicate that processors are part of an integrated circuit, we say they are embedded.
Details of the network processor and each of its processors are irrelevant. The important point is to understand that more detail is revealed at each architectural level. In this case, we have seen that although a single integrated circuit can contain many functional units, the structure of the circuit is only revealed in a chip-level diagram; the chip structure remains hidden in a board-level diagram. We can summarize:
Each level of an architecture reveals details that are hidden by higher levels. A chip-level architecture specifies the internal structure of an integrated circuit that is hidden in a board-level architecture.
11. Structure of Functional Units on a Chip
As a final example of architectural levels, we will examine how it is possible to describe the architecture of one component on a chip. FIG. 7 shows the SRAM ac cess unit from FIG. 6. The internal structure of the memory access unit is quite complex.
12. Summary
The architecture of a digital system can be viewed at several levels of abstraction.
A system-level architecture shows the structure of an entire computer system, a board level architecture shows the structure of each board, and a chip-level architecture shows the internal structure of an integrated circuit. At each successive level, details are revealed that remain hidden in previous levels.
As an example, the section presents a hierarchy of architectures that shows the structure of a personal computer, a Wi-Fi network interface board in the computer, and a network processor on the interface board. Finally, we saw that a chip-level architecture can be further refined by looking at the architecture of each embedded unit.
A more advanced version of the chip provides sixteen microengines.
FIG. 7 The internal structure of the SRAM access unit that remains hid
den in FIG. 6. Each successive level in the architectural hierarchy reveals
further details and structure.
EXERCISES
1. If an engineer is offered a job as a system architect, what will the job entail?
2. What is the motivation for a computer that offers two buses?
3. A computer with a USB port contains hardware known as a USB hub that usually connects the external ports to a PCI bus. Modify the diagram in FIG. 2 to show a USB hub.
4. If a computer contains two buses connected by a transparent bridge, and the memory connects to one bus while the devices connect to the other, will the devices be able to communicate with memory? Explain.
5. What is the purpose of a controller chip in modern bus architectures?
6. A computer has one device that uses an old bus, but does not have the normal sockets or wires for the bus. How is such a situation possible?
7. In a PC, would a super high-speed video system connect to the Northbridge chip or the Southbridge chip? Explain.
8. If it takes 40 seconds to transfer a video over a USB 3.0 port, approximately how long will it take to transfer the same video over a Wi-Fi network that operates at 20 megabits per second?
9. A network processor, such as the one shown in FIG. 6, is classified as a System on Chip (SoC). Explain why.
10. In many hardware design documents, rectangular boxes are used to represent a subsystem. Can one tell by looking at the diagram approximately how many gates will be needed to implement the function the box represents? Explain.
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