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Microcontrollers generally have built-in I/O terminals that can be directly connected to low voltage, low-current peripherals. It is usually necessary to provide I/O ports to interface a microprocessor system to its peripherals. The ports may operate as parallel or serial interfaces.
Ports may be built from TTL or CMOS logic or special ICs are available, such as the Z80 PIO and the Z80 SIO. Other I/O ports are discussed. To interface a digital system to an external analogue system there are analogue to digital converters for input to the digital system and digital to analogue converters for output. ADCs include flash converters and successive approximation converters. The DACs are represented by an R-2R converter.
A microelectronic system needs some way of communicating with the outside world. It needs input, by which it receives data and is told what to do. It needs output so that the processing of the data can have some useful result. Microelectronic systems communicate with the outside world through ports.
We have already seen that a microcontroller, such as the '1200' has two ports on its chip, known as Port B (8 bits) and Port D (7 bits). The bits of each port are individually programmable as inputs or outputs. Each port has a data direction register (DDR) where a series of 1s and 0s determine whether a bit is an input or an output. The DDR has an address in the memory space of the microcontroller. The program writes values into the DDR to set the pins as inputs or outputs.
For example, if the value 11000000 is written into the DDR for Port B, the top two lines (B6 and B7) are set as outputs and the remaining lines as inputs.
As outputs, each line of the '1200' ports is able to sink 20 mA when the output is logic level low. When the output is high, it is able to source up to 4 mA. These figures assume that the IC is running on a 5 V supply. Provided the design keeps to these limits and that the total current sunk by the port is not more than 80 mA, it is safe to drive external circuits directly from the port. Some simple examples of this are shown in Figs. 2.6 and 2.7. In Fig. 2.7 we have not driven the filament lamp directly because such a lamp may require 60 mA or more. Instead, we have used a transistor as a switch, with resistor to limit the base current to a safe level.
FIG. 1 A DC input interface of a PLC has an opto-isolator to allow
the microcontroller to operate on an entirely separate DC supply, usually
at lower voltage and free from noise. Here the sensor is a switch which
might, for example, be a physical limit switch, a pressure switch, a tilt
switch, or attached to a float. A PLC input card usually has 8 or 16 channels
identical to the one shown here.
As already mentioned, the sensors and actuators used in industrial applications often operate at voltages greater than that used for powering the microcontroller or may require current greater than a microcontroller output port can provide. It may be necessary to interface the microcontroller to AC circuits, and to circuits carrying an excessive amount of noise (see SECTION 6). PLCs have input and output interfaces that isolate the microcontroller. FIG. 1 is the circuit of a DC input interface. Similar precautions are taken in the circuits for DC output and for AC input and output.
A microprocessor does not have input and output ports. Instead, it connects with the other parts of the system through the data bus.
However, the data pins of a microprocessor are not necessarily capable of sourcing or sinking sufficient current to drive the large number of devices that may be attached to the bus. Additionally, a system such as a microcomputer may be designed so that the CPU can drive the internal peripherals (keyboard and disk drives, for example), but could not be capable of driving external devices (printer and scanner, for example) that may be added to the system. Ports must be attached to the data bus to interface it to external devices.
Ports may be built from ICs belonging to the 74XX and CMOS families, or we may use special ICs intended to interface with particular CPUs. Ports are divided into two types:
• Parallel ports
• Serial ports
Parallel ports
The difference between parallel and serial transfer is explained in Figs. 2.2 and 2.3. Parallel ports are used where there is a large amount of data to be transferred and when the peripheral is not far from the CPU.
For example, a printer is connected to the system by a parallel port. A serial port would be too slow for this application. Serial ports are used for long-distance communication, such as sending data by telephone.
They may also be used where speed is not of prime importance and the complexities of having 8 parallel lines is best avoided. For example, a program is downloaded from a computer into a microcontroller using a serial port. Another example is a digital camera, where the image is fed to a computer through its serial port.
Parallel ports built from TTL
A port could be built from individual TTL gates but, more often, we use members of the TTL family specially designed for interfacing to microelectronic systems. One such IC is the 74244 octal buffer. To make the diagram simpler, we have drawn only one of the eight identical buffers. The function of the buffers is to make more power available for driving external devices. A typical TTL output of the 74LSXX series can sink up to 8 mA when the output is low. It can source up to 0.4 mA when the output is high. By comparison, for a buffer in the same series, the currents are 24 mA and 2.6 mA.
Note that the buffer shown in FIG. 2 is logic TRUE, or non-inverting.
The output level is always the same as the input level. Inverting buffers are also available and may be useful in certain circumstances.
Buffers are used:
• as data output buffers. The inputs are connected to the data bus and the outputs to a data output socket or to the input of a peripheral device. The three-state outputs are normally not required in this application so the ENABLE pins are connected to the positive supply through a resistor. The peripheral device can read from the data bus at any time.
• as data input buffers. The inputs are connected to a data input socket and the outputs to the data bus. The outputs are enabled by a line from an address decoder only when the buffers are to place data on the bus.
• as address bus buffers. If there are many address decoders on the address bus, the CPU address outputs may not be able to drive them all. Instead, the CPU address outputs go to a buffer and from there the bus continues to the decoders.
Another type of port IC is an octal latch. An example is the 74LS373 illustrated in FIG. 3. This allows data to be stored (latched) at any time by making the ENABLE LATCH input low. In an input port, data from the peripheral can be latched at the instant the peripheral is ready to deliver it. The data is placed on the bus whenever the CPU is ready to receive it by making the ENABLE OUTPUT input low. Similarly, in an output port, data from the CPU can be transferred to a peripheral when the peripheral is ready.
A third type of port uses an octal D-type flip-flop, such as the 74LS374. The pinout of the IC is the same as that of the 74LS373 (Fig 5.3) except that the EL input is replaced by a clock input.
FIG. 2 The 74244 IC contains eight identical buffer gates with 3-state
outputs. The outputs are enabled in two groups of four gates when the two
ENABLE inputs are made low.
FIG. 3 There are eight identical latches in the 74373, each with a
data input (D) and a 3-state output (Q).
The latches are all controlled by the ENABLE LATCH and ENABLE OUTPUT inputs.
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Latches and flip-flops
Both of these are data storage devices but they act in slightly different ways:
Latches: There may be several (often 8) latches on the same chip and these are all controlled by the STORE or LATCH ENABLE input. While the STORE input is high, data at the output of each latch follows the data at the in put. When the STORE input is made low, data present at the output at that instant remains unchanged. It remains unchanged until STORE goes high again, when it then follows input again.
Some types of latch have three-state outputs. Some latch when the STORE input goes high, instead of low.
Flip-flops: The type used in ports is the D-type and there may be several (often 8) on the same chip. They are con trolled by the CLOCK input. Data at the output of the flip flop remains unchanged until the CLOCK input goes from low to high. The data present at the input at that instant is then transferred to the output. There is no stage at which output follows input, as in the latch.
Sumamry:
Latches follow or latch.
D flip-flops change only at the clock edge.
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We may also build a port using an octal bus transceiver. As the name implies, they provide two-way buffered communication between two busses. One may be the internal data bus of a computer; the other may be the bus of a microelectronic system interfaced to the computer.
Control inputs set the device to operate in one direction or the other.
The 74LSXX ICs mentioned in this section are also available in CMOS versions.
Parallel port ICs
There are several different types of parallel port IC with very similar features and a few minor differences. FIG. 4 shows an IC intended for use with microprocessors of the Z80 family, the Z8420, more usually known as the Z80 PIO (parallel I/O).
Fig 4 illustrates the more important features of the Z80 PIO. It has a bi-directional connection with the system data bus which is 8 bits wide. It has two 8-bit ports, referred to as Port A and Port B. Each port has two handshaking lines for communicating with devices attached to the ports. The lines are RDY (ready) and STB (strobe).
FIG. 4 The Z80 PIO provides two ports which may be configured as inputs
or outputs. The decoder enables the IC when the upper six bits of an address
in the range $F0 to $F3 is presented to it. Inputs marked with small circles
are active-low.
The PIO operates in one of four modes for each of the ports:
Mode 0 As an 8-bit output port
Mode 1 As an 8-bit input port
Mode 2 As an 8-bit bidirectional port (Port A only)
Mode 3 Port B as a bitwise I/O port when Port A is in mode 2.
Each port has a port control register to which a byte is sent to select the mode. If the port is programmed as mode 3, a second byte must be sent to define which bits are inputs and which are outputs.
The port registers and port control registers are allocated a range of four addresses. These are fixed addresses which are automatically put on the bus by the Z80 CPU when accessing the port. They can not be chosen by the user. The addresses are:
$F0 Port A data register.
$F1 Port A control register.
$F2 Port B data register.
$F3 Port B control register.
All four addresses have the same top six bits (111100). The decoder circuit receives address lines AB2 to AB7 and makes the CE input low when these carry 111100. The register selected depends upon the bottom two bits, AB0 and AB1 which go directly to another decoder inside the PIO.
In Mode 0 (the port as a data output), the CPU writes data into the data register. This causes the RDY output to go high, which tells the peripheral that there is data in the register waiting to be read. The peripheral reads this data when it is ready to do so, and then puts a low pulse on the STR line. This tells the PIO that the data has been read and this message must now be passed on to the CPU. The PIO first makes the RDY output low, as there is no new data to read. Then the INT output of the PIO is made low. This interrupts the CPU, which is programmed to respond in some way, usually to send the next byte of data. By using this simple handshaking procedure, successive bytes of data are transferred from the CPU to the PIO and then to the peripheral.
A similar technique is used in Mode 1 (the port as a data input). If the PIO is ready to receive a data byte from the peripheral, its RDY output is high. The peripheral puts data on the port bus, then sends a low pulse on the STR line. This latches the data in the port register. The RDY line is made low so that the peripheral does not send another byte until this byte has been read by the CPU. The STR pulse causes the PIO to interrupt the CPU by putting a low level on the INT line. The CPU is programmed to read the data from the register when it is interrupted.
The control signals at the end of the read operation cause the RDY line to go high, indicating to the peripheral that it can now send the next byte.
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Other parallel port ICs
There is a wide range of parallel port ICs available, similar to the Z80 PIO, but usually specialized to work best when connected to one particular CPU.
The 8255A PPI (programmable parallel interface) has three 8-bit ports programmable as inputs or outputs. The individual pins can not be programmed, but the high and low nybbles of Port C can be programmed separately.
Handshaking is provided. The PPI has the same addressing as the Z80 PIO, except that addresses $F0 to $F2 cater for the three ports and all control signals go to $F3. As in the Z80 PIO, all mode control operations involve sending a byte to the control register. The bit set/reset mode is of interest. It allows the bits of Port C to be set or reset. Only one bit can be set or reset at one time. This feature is useful for producing strobe signals.
The Intel 68230 PIT (parallel interface timer) is designed for 68000 systems. Port A and Port B are both definable as 8-bit input, output or bidirectional ports. Alternatively, they may be combined as a single 16-bit input, output or bidirectional port. The ports may also be programmed for bitwise operation. There is a set of lines for handshaking.
There is a third port, Port C, which can be used as a I/O port but many of its pins are multiplexed for other functions, including acting as input and output for the on-chip timer.
The timer is a 24-bit counter that has a value loaded into it and then counts down. Depending on the programming, it triggers various events when the count reaches zero. The timer can be programmed to generate periodic interrupts, a square wave of selected frequency, or a single interrupt after a preset period of time. In addition to these functions, it can be used to measure elapsed time. As is usual with such devices, the timer is programmed by the CPU writing codes into its registers. The registers can also be read to discover, for example, the length of time elapsed since it was reset.
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The above description shows how the data is transferred with hand shaking, so that (if inputting) the CPU will not miss any data. Conversely, when outputting, the CPU will not send any data until the previous byte has been acknowledged. These procedures can be simplified in some circumstances. At an input port, the STR line can be held permanently low (perhaps connected directly to the 0 V line).
Then any data that the peripheral sends appears immediately in the register and can be read by the CPU at any time. For example, the peripheral could be a DAC, continuously providing data, which is sampled by the CPU at regular intervals. The output routine may similarly be simplified. Data sent by the CPU is always immediately latched into the register and can be read by the peripheral at any time.
The peripheral reads the data whenever it needs it, ignoring the RDY line and not signaling back on the STR line. The INT routine is disabled in the CPU so that it sends data whenever it has data to send.
In Mode 2, Port A is bidirectional, and four handshaking lines are available. The operating method is a combination of the input and output sequences described above. When Port A is in mode 2, Port B must be assigned to Mode 3, the bitwise I/O. There is no handshaking on Port B in this mode. Signals placed on the output pins by the CPU go straight out to the peripheral. Signal placed on the input pins by the peripheral are put on to the data bus when the PIO is enabled. In Mode 3 it is possible to configure all eight lines in the same direction, in which case the port becomes an input or output port with no handshaking. Alternatively, the pins may be configured separately and up to eight 1-bit inputs or outputs may be connected to the port.
Serial ports
For transmission of data over short distances of a meter or two, an ordinary TTL or CMOS gate or buffer can be used. Additional gates are needed if any handshaking signals are to be transmitted as well.
For longer distances it is preferable to use a serial port based on the RS-232 standard. This allows for transmission over distances up to 15 m. The driver output signal is between ±5 V and ±15 V. The maximum data rate is 20 Kbit per second. Other RS standards exist for higher rates of transmission. The RS standards specify the types of connector to be used and the functions of each signal line.
The standard specifies the use of nine lines for carrying the serial signal and the handshaking signals. FIG. 5 shows the connections between a transmitting computer and receiving device, such as a modem. A 25-pin D-type connector is used at both ends of the cable.
More recently, a 9-pin D-type connector has been used. The pin connections are:
When using a 25-pin socket there is often a line called Protective Ground connected to the metal chassis of the terminal at either end.
This uses pin 1. TD is sometimes known as TXD and RD as RXD. SG is sometimes called GND.
In practice, many systems use the 9-pin connectors with only three lines, TD, RD and SG for two-way communication. One-way connection needs only two lines; TD at the transmitting end is wired to RD at the receiving end.
Interfaces can be built from TTL gates, as in Figs 5.5 and 5.6. The TTL input to the interface (FIG. 5) comes from the transmitting system, possibly through its output port. The voltage levels of the system are 0 V (= logic 0) and +5V (= logic 1). The 74LS06 gate inverts these levels. Note that the gate has an open collector output, requiring a pull-up resistor. At this stage, the voltage for logic 0 is higher than that for logic 1. As the signal passes through the circuit it is inverted by each of the transistors so is still inverted at the output. Here the levels are ±12 V, with +12V being equivalent to logic 0 and -12 V being equivalent to logic 0. These levels are valid RS232 levels.
FIG. 5 This interface converts a TTL signal (0 V = 0, +5 V = 1) to an RS232
signal (-12 V = 1, +12 V = 0).
FIG. 6 The INVERT gate used in this RS-232/TTL interface has an open-collector
output.
At the receiver, the signal first passes through a network comprising a resistor and two diodes to limit the voltage swing to between 0 V and +5 V. This is fed to the 74LS06 gate which inverts it, so restoring the original logic levels. Now +5V again corresponds to logic 1, and 0 V to logic 0. Once again, the gate needs a pull-up resistor. Its TTL signal may now be fed to any TTL input, including the input port of the receiving system.
A number of ICs are available for transmitting and receiving RS-232 signals. An example is the MAX232 IC, which provides for two RS-232 lines in each direction. In includes a voltage-doubling circuit to generate +10 V from the +5 V supply. This means that only the usual +5V supply is needed to produce the RS-232 levels in the chip. It also includes an inverter circuit to generate -10 V. The IC has two TTL to RS232 inverter gates and two RS232 to TTL inverter gates.
When data is being sent without using handshaking lines, it is important to have a protocol for data transmission. RS-232 does not include any such protocol but there are a number of data transmission proto cols agreed by international bodies. These are used not only for RS-232 transmissions but for other interfacing techniques as well. In one of the more common procedures, a transmitter that is waiting to transmit is in the 'marking' state. Its output signal is at a continuous low level (FIG. 7). As soon as it has data to transmit, it places a high pulse on the line. This is called the Start pulse and warns the receiver that a message is about to arrive. Immediately after the Start pulse, the transmitter sends eight data bits, of length equal to the start pulse.
These may be low level or high level, and are followed by a low Stop pulse. After this, the transmitter may send another Start pulse followed by the next byte of data, or it may remain in the 'marking' state for a while if there is nothing to send.
FIG. 7 This serial interface protocol is called asynchronous be cause
it does not need the transmitter and receiver to have their sys tem clocks
synchronized. In some systems the Stop bit must be at least two bit-periods
long.
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Bit rate and baud rate
Both of these are used to express the rate of transmission of data. They are not the same thing.
Bit rate is the number of binary bits (0's or 1's) transmit ted in 1 second. Faster transmission rates are often ex pressed as kilobits (1024) bits per second.
Baud rate is the number of 'signal events' transmitted per second. If one signal event (for example, a pulse of given length or amplitude) represents one binary digit, the baud rate and the bit rate are equal. But in many systems a signal event represents more than one bit.
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The eight data bits usually consist of seven data bits, D0 to D6 followed by a parity bit (see box). For data to be read correctly, the transmitter and receiver must both be operating at the same baud rate.
However, there is no need for precise timing because each group begins with a Start pulse, which resets the clock of the receiver. It then has to keep time for only 8 pulses. This method of signaling is described as asynchronous, because it does not require the clocks at the transmitter and receiver to be permanently synchronized.
FIG. 8 A shift register is used to convert parallel data into serial
data, ready for transmission by a serial output interface.
This is a parallel in serial out (PISO) shift register.
Data is processed in parallel form in microelectronic systems. Before it can be sent to a serial interface such as the one shown in FIG. 5 it must be converted to serial form. There are several ICs that can do this, including the 74LS165 parallel-serial converter. This IC is described as a shift register (FIG. 8). It has 8 registers, A to H, each of which holds one bit of data. The registers are connected internally so that the data in one register can be shifted into the register on its right. It has 8 data inputs which, in a computer, could be connected to the data bus.
When its LOAD input is made low, the data present on each data line is loaded into the corresponding register. The IC has a data output and an ENABLE input. If the ENABLE input is held low, the data is shifted one step to the right every time the clock input rises from low to high. On the first rising clock edge, the data in H (D0, equal to 0 or 1) appears at the serial output terminal and can be sent to a serial output interface. The data in G is transferred to H, and the other transfers are F to G, E to F, D to E, C to D, B to C, and A to B. Each bit has been shifted one place to the right. On the next rising clock edge, D1, originally in G but now in H, appears at the serial output and goes to the output interface. The other data bits are shifted one step to the right. The process repeats for the next six clock edges, the bits appearing at the serial output in order D2, D3, D4, D5, D6, and D7.
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Parity
This is a technique for detecting errors in transmission.
When a group of 7 data bits is transmitted the number of 1's is counted and an extra bit, the parity bit is added at the end, so that the total number of 1's is even.
Examples:
If the seven bits are 1101010, the group already contains an even number of bits. So the parity bit is 0 and the group transmitted is 11010100.
If the seven bits are 0110111, the group contains an odd number of bits. The parity bit is 1, to make the number of bits even. The group transmitted is 01101111.
The receiving system counts the number of bits in each group and rejects any group that contains an odd number.
Then the parity bit is removed from the end of the group and the remaining seven bits are sent on for processing.
The receiver may be able to request the transmitter to send any rejected groups again.
This technique is known as even parity. Some systems use odd parity, in which the number of 1's is made up to an odd number.
Parity checking will detect a single error in a group, but does not detect two compensating errors. Adding a parity bit to each group means that the rate of data transfer is slightly reduced.
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More on parity
Other more complicated systems of parity checking have been devised. In the system outlined below, 16 bits of data are arranged in four groups of four, and a parity bit is added to each row and column. Five groups of five bits are transmitted instead of four groups of four. This means that the rate of data transfer is reduced, but there are advantages.
Example:
This example is worked with even parity.
In the table above, it can be seen that the parity is wrong for the second column and the third row. This locates the incorrect bit, which is in the shaded box. The analysis locates the incorrect bit, which can then be changed automatically, to a 1 in this case. There is no need to repeat the transmission.
This technique also checks that the parity bits have been received correctly:
Parity is wrong in the 2nd row and 5th (parity) column.
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At the receiving end of the transmission, the serial data must be re-formatted into parallel data so that it can be processed further. Here we need a serial-to-parallel converter, such as the 74LS164 (FIG. 9).
This has a serial input and eight data outputs. The way it works is the converse of the previous shift register. Data is clocked in starting with D0 and ending with D7. D0 is first stored in register A. As clocking proceeds D0 is right-shifted along the registers until it reaches register H, with all the other bits in order along the chain. Then the whole byte is unloaded through the eight parallel outputs. The data can be fed directly to a device such as a decoder that controls a 7-segment LED display. If it is to go on to a data bus, it must first be stored in a set of latches with three-state outputs.
FIG. 9 Received serial is converted back to parallel form by a serial
in parallel out (SIPO) shift register.
Shift registers perform the essential conversion between serial and parallel data but in most systems it is necessary to add start, stop and parity bits before transmission. On reception, it is necessary to remove the start and stop bits, to check parity and finally remove the parity bit.
Although parity checking ICs are available, the logic circuit required for this degree of processing is very complicated and it is easier to use a ready-made IC. Most CPU families include a serial output interface IC that accepts parallel data and produces serial data complete with the additional bits. They also accept serial data, check its parity and produce a parallel output.
The Z80 SIO (serial input/output) is an IC that includes all the necessary facilities on the same chip (FIG. 10). The SIO is a very versatile IC and has several operating modes. We will look at the features that are of general interest. The SIO has two channels, A and B that are separately programmable. As with the PIO, the CPU communicates with the IC as if it consists of four registers, a data register and control register for Channel A, and the same for Channel B. The CPU controls the SIO by writing bytes into the control registers.
FIG. 10 Comparison with FIG. 4 shows that many of the connections
of the Z80 serial input/output device are the same as for the Z80 PIO. In
the right the figure shows only Channel A. The lines of Channel B are identical
except that it has no TxC and RxC inputs.
Both channels share the baud rate generator.
With serial communications it is essential that both the transmitting station and the receiving station are set to receive data at the same rate.
This is usually specified by stating the baud rate. There are a number of standard baud rates, ranging from 110 to 38400. The baud rate generator may be a simple crystal-controlled TTL oscillator or there is the Z80 CTC generator. Also available are special baud rate generators such as the MC14411. The timing chain of the SIO can be set to divide the pulse rate by different amounts so that it is possible to send and receive at a selection of baud rates without having to change the clock.
The SIO can be programmed (by coded bytes written into its control registers) to operate according to a number of different protocols (see FIG. 7). It is possible to select for a character of 5, 6, 7, or 8 bits, and to add 1, 1½, or 2 stop bits. It is also possible to choose between even parity, and to disable the addition of a parity bit if preferred.
If the system is to communicate with another system by way of the public telephone network, it is necessary to use a modem. This is a device which receives a serial transmission of high and low logical levels (as in FIG. 7) from the SIO and converts it into a form suitable for transmission over the telephone line. This is known as modulation.
The demodulator section of the equipment converts the received modulated signal back into pulses at high and low logic levels. One modulation technique is frequency shift keying (FSK). The logic lows and highs of the serial data are represented in the modulated signal by two different audio frequencies. For example, in the Kansas City protocol, a 0 is represented by four cycles at 1200 Hz, and a 1 is represented by eight cycles at 2400 Hz. Thus, each bit takes the same length of time to transmit. Control signals between the SIO and the modem of each channel are sent by way of four handshaking lines.
There are also two lines for sending and receiving the serial data.
Data converters
Some systems need to be able to accept analogue input. The input (usually a voltage) varies smoothly over a given range. The output must be a digital quantity. For this purpose, the input interface includes an IC known as an analogue-to-digital converter or ADC. Examples of systems needing an ADC for input are audio systems (such as a digital tape recorder) and many instrumentation systems (such as a digital multimeter).
There are several types of ADC, but the two most popular types are flash converters and successive approximation converters.
Flash converters
Flash converters are faster than the other types but have the disadvantage of being more expensive than other converters with comparable precision. FIG. 11 demonstrates why. A flash converter consists of a number of comparators connected by their inverting (-) inputs to a chain of resistors. The chain of resistors is connected at one end to 0 V and at the other end to a reference voltage. This produces a fixed range of voltages along the chain. The input voltage is fed to the non-inverting (+) inputs of all the comparators. Each comparator compares this voltage with the voltage it is receiving from the chain. The outputs of the comparators then swing either low (0) or high (1), depending on whether the input voltage is less than or greater than the voltage from the chain. The result of this is that, as the input voltage increases from 0 V, the outputs become 0000000, 0000001, 0000011, 0000111, and so on, to 1111111. There are 8 possible outputs, which are sent to a priority encoder. This is a logic circuit which determines which is the highest '1' bit (counting from the LSB on the left, that is, from the bottom of the chain). The output of the encoder ranges through all the binary values from 000, 001, 010, 011, and so on to 111. This output is proportional to the input voltage, and the conversion of analogue to digital is complete.
FIG. 11 A flash analogue to digital converter is based on a chain of
resistors connected to an array of comparators.
The conversion time of a flash converter is the time taken for the comparators to settle, plus the propagation delay in the gates of the encoder. Typical conversion times lie in the range 10 ns to 2 µs, which is fast enough for the conversion of audio signals in real time.
The ADC of FIG. 11 has seven comparators and there are only 8 possible output readings. This has to cover the entire input range from 0 V up to the reference voltage. As a simple example, if the reference voltage is 8 V, the eight possible values from the encoder correspond to 0 V, 1 V, 2 V, … , 8V. We can read the voltage only to the nearest 1 volt. If we want higher precision, we must have more comparators.
The rule is that, given n comparators, the number of possible steps in the output is 2n - 1. For example, a flash ADC with 8-bit output requires 256 converters. Such an ADC often has a 2.56 V reference, so that each step in the output is 0.01 V.
Flash ADCs are made with 4-bit outputs and 8-bit outputs for low precision applications. For higher precision there are 12-bit converters, but these work by a technique known as half-flash. This is a compromise that requires fewer comparators. It works in two stages and therefore takes longer.
Successive approximation converters
These provide greater precision than flash converters at relatively low cost. Converters with 16-bit precision are available. Conversion times of 20 µs are achieved by some types, though some take as long as 100 µs.
FIG. 12 At each stage of conversion, the analogue equivalent of the
output value in the SAR is compared with the analogue input voltage.
Fig. 12 illustrates the principle on which the successive approximation works. This example has only four bits, to make the explanation easier. Conversion takes place in a number of steps, one per clock cycle. As the name suggests, the converter works by gradually homing on the correct output. To begin, the START CONVERSION input of the IC is made low. At the next clock step, the control logic sets the first bit (the MSB) of successive approximation register (SAR) to '1'.
In other words, the first approximation (or guess) at the correct output is '1000', the 'half-way point'.
There is a digital-to-analogue converter that converts this approximation to the equivalent analogue voltage. This is then compared with the input voltage. If the guess is less than the input voltage, we know the approximation is too low. The MSB stays at '1' and the control logic goes on to try the next digit. If the guess is more than the input voltage, it is too high. The MSB is reset to zero, and the logic goes on to try the next digit.
If the guess is too low, setting the next digit gives 1100 from the SAR.
This too is converted and tested against the input voltage. Again, the digit is either retained as '1 'or reset to '0'. The routine is repeated at each clock cycle, working along from the MSB to the LSB. After 4 cycles, conversion is complete and the END OF CONVERSION output of the IC goes high. The data is then present on the parallel outputs of the converter. With some ADCs, the data is presented at a serial output, MSD first. The time taken for the conversion is roughly proportional to the number of bits in the output, so higher precision is obtained at the cost of longer conversion time.
One of the problems with successive approximation is that a rapidly changing input may be impossible to evaluate. The homing routine does not work properly with a moving target. If this is a problem, a sample and hold circuit is used to sample the input voltage and hold it while it is being converted.
Digital-to-analog converter
A system that has processed data in digital form may need to output it in analogue form. For example, the circuit of a CD player has to output an audio signal, which is an analogue quantity. This requires a digital to-analog converter, or DAC. There are several types of DAC but the commonest is based on the R-2R ladder. FIG. 13 shows a 4-bit example. The switches are actually CMOS switches under logical control.
The most frequently used DACs depend on a resistor network usually known as an R-2R ladder. Typically, R equals 10 k-Ohm. There are CMOS switches S0 to S3 in each 'rung' of the ladder which can be switched either to the 0 V line or to the inverting (-) input of the operational amplifier. Whichever way a switch is set, the same current flows out from the rung, so the currents flowing in the network are not affected by which switches are open and which are closed. A short calculation shows that the current flowing out of a 'rung' is equal to half of the current flowing out of the 'rung' to its left. For example, if the reference voltage is 5 V, and 2R is 20 k-Ohm, the current flowing through S3 (the MSB switch) is 250 µA. The current flowing through the other 3 switches is 125 µA, 62.5 µA and 31.25 µA. The currents through switches S3 to S0 are proportional to the values of the corresponding bits D3 to D0 in a 4-bit binary number. Similarly, the sum of the currents is proportional to the sum of the bits. In the figure, S3 and S1 are switched to the op amp, so the equivalent binary number is 1010, and the sum of the currents is 250 + 62.5 = 312.5 µA.
The op amp is connected as an inverting summer. Its output swings negative by an amount proportional to the sum of the currents. It takes only a second inverting amplifier with a fixed gain of -1 to make the output positive. The output appears as a voltage, proportional to the reference voltage.
R-2R DACs convert in the short time it takes for the logic to set the switches and for the op amp to settle. DACs are available for inputs up to 16 bits wide, and a settling time often less than 1 µs.
FIG. 13 The R-2R 'ladder' produces currents that are weighted on the
binary scale. They are summed by the operational amplifier.
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Precision
The precision of the flash and R-2R converters depends on the precision of the resistors. Their exact values do not matter but it is important for the ratios between them to be exact. This is relatively easy to achieve because all the resistors are fabricated at the same time on the same chip.
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EXERCISE 1 -- ADCs
Study the data sheet of an analogue to digital converter and note its main operating conditions. Set up the ADC on a breadboard and provide it with:
• A suitable power supply.
• A variable input voltage for conversion.
• A set of 8 LEDs switched by transistors to display the digital output.
• If it is a successive approximation converter, it will need a clock pulse generator, a low pulse generator at the START input (use a 10 k-O resistor to pull the pin up to +5 V, and connect a push-button between the pin and 0 V). Use an LED indicator on the EOC output.
The data sheet may describe other connections that should be made.
Make conversions at a number of input voltages between 0V and the supply voltage. Plot a graph of the digital out put reading against the analogue input voltage. Comment on the curve you obtain.
EXERCISE 2 -- DACs
Study the data sheet of a digital to analogue converter and note its main operating conditions. Set up the DAC on a breadboard and provide it with:
• A suitable power supply.
• A set of 8 switches to provide each data input with 0V or the positive supply voltage.
• A multimeter to measure the output voltage.
The data sheet may describe other connections that should be made.
Make conversions at a number of digital inputs between 0 and 255 (assuming an 8-bit input). Plot a graph of the analogue output reading against the digital input. Comment on the curve you obtain.
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Interfacing to a PC
When we interface to a computer, we are not connecting directly to the CPU as described in other parts of this SECTION. The computer is a complete microelectronic system and it has ports to which we can connect external circuits of our own design. The PC usually has one parallel port and one serial port, though some models may have more.
The most appropriate port for the interfacing projects described in this guide is the parallel port, usually known as LPT1. This is the port to which a printer is normally attached. It may have other devices daisy-chained to it, such as an external disk drive.
The standard parallel port has a D-type 25-pin socket on the rear of the computer. The pins of this socket are allocated to three ports, as shown in FIG. 14. There are eight ground lines, of which one must always be connected to the 0 V line of any device attached to the computer.
As might be expected, the ports are allocated addresses in the PC's memory space. To output and input data we send it to the address of one of the ports. Using a high-level language, we do not have to deal with data direction registers or with handshaking. All this is taken care of by the machine code generated by the running of the program. In SECTION 10 there are some programs which demonstrate how this is done using BASIC.
FIG. 14 The parallel port of a PC is seen as a 25-pin socket. It has
pins for three ports and eight ground lines. In the figure the socket is
viewed from the rear, as you see it when you are about to plug in the printer
cable.
This table shows the addresses used for sending or receiving data from the three registers:
The correct address to use can be found by looking in System Information.
Referring to FIG. 14, the pins of the 8-bit register are as follows:
After data has been loaded into this register, it can be read back to check it.
The 4-bit output register is more complicated. It is an 8-bit register but the lower 4 bits are not used for data output:
Bit 7 is inverted. If its input line is low, D7 equals 1. This bit causes an interrupt when it is made high (that is, its input line is made low).
However, it does not do this if it is disabled by making bit 4 of the 4-bit I/O register low.
The 4-bit I/O register has the following pin allocations:
Bits 0, 1, and 3 are inverted. Bit 2 is normal. To use this register as input, all bits D0 to D3 must first be made high. Then input data either pulls the bit register low, or leaves it high. It is then read.
8-bit output 4-bit input 4-bit I/O
Apart from the complications mentioned above, the ports are suitable for the 1-bit interfacing described in SECTION 10. For more extensive interfacing there are I/O cards that can be plugged into slots inside the computer, and which have their own special addresses and decoding circuits.
Problems on interfacing
1. Describe and compare two different output interfaces.
2. Describe and compare two different input interfaces.
3. List and describe the characteristics of three TTL devices that can be used as input/output ports.
4. Explain how you would use a Z80 parallel input/output IC (or any named device that is similar) to interface a microprocessor to (a) a printer and (b) a 4-key keypad.
5. What hardware would you use to send signals from a CPU over the telephone network?
6. What is an analogue to digital converter? How would you interface it to a named processor? Give an example of a practical use for such a circuit.
7. Describe how you would interface a digital to analogue converter to a named processor.
8. Explain the difference between a latch and a flip-flop.
9. Describe the action of a shift register. For what purposes are shift registers used in microelectronic systems?
10. Explain the difference between bit rate and baud rate. When are they equal?
11. What is meant by parity? How and why is it checked in serial data transmission?
12. Describe a method for interfacing devices to a personal computer.
How could you use this interface to receive data from an ADC?
Multiple choice questions
1. When it has a logic low output, a TTL gate can sink up to:
A 24 µA.
B 8 mA.
C 1 mA.
D 16 µA.
2. Buffers are used is certain systems because they:
A prevent voltage spikes from passing.
B change state very rapidly.
C change a logic high to a logic low.
D sink and source larger currents.
3. The RS-232 standard covers serial transmission for distances up to:
A 15 m.
B 1 km.
C 200 m.
D 8 m.
4. Which of these does the RS-232 standard not specify?
A Serial signaling protocol.
B Types of connector.
C Maximum frequency.
D Allocation of connector pins.
5. A shift register:
A converts parallel data to serial data.
B moves bits from one register to the one next to it.
C has three-state outputs.
D converts serial data to parallel data.
6. In an even-parity system, which one of these bytes is in error?
A 11001100.
B 11110011.
C 01101011.
D 00110101.
7. An R-2R 'ladder' is used in a:
A DAC.
B flash converter.
C successive approximation converter.
D operational amplifier.
8. One of the disadvantages of a successive approximation converter is that:
A it is very expensive.
B the input must not change too fast.
C its output is limited to 8 bits.
D it is inaccurate.
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