ESD--Electrostatic Discharge

1. ELECTRICITY AND ELECTROSTATICS DISCHARGE

1.1 Electricity and Electrostatics

In the field of electricity, electrostatics, and circuit theory, there are many discoveries and accomplishments that have lead to the foundation of the field of electrostatic discharge (ESD) phenomenon. Below is a chronological list of key events that moved the field of electrostatics forward:

_ 600 B.C. Thales of Miletus discovers electrostatic attraction.

_ 1600 A.D. William Gilbert proposes the ''electric fluid'' model.

_ 1620 A.D. Niccolo Cabeo discusses ''attractive'' and ''repulsive'' phenomena.

_ 1729 A.D. Stephen Gray demonstrates ''electricity'' can be transferred by wires.

_ 1733 A.D. Charles Francois du Fay discusses two kinds of electricity-''resinous'' and ''vitreous.''

_ 1749 A.D. Abbey Jean-Antoine Nollet invents the two-fluid model of electricity.

_ 1745 A.D. Pieter Van Musschenbroeck invents the Leyden jar, or the capacitor.

_ 1747 A.D. Benjamin Franklin proposes single fluid model, with ''positive'' and ''negative'' charge.

_ 1748 A.D. Sir William Watson develops the first ''glow discharge.''

_ 1759 A.D. Francis Ulrich Theodore Aepinus discusses ''charging by induction.''

_ 1766 A.D. Joseph Priestley deduces the electric force follows an inverse square law.

_ 1775 A.D. Henry Cavendish invents the concept of capacitance and resistance.

_ 1785 A.D. Charles Augustin Coulomb verifies the inverse square law relationship.

_ 1812 A.D. Simeon Denis Poisson demonstrates that charge resides on the surface of a conductor.

_ 1821 A.D. Humphrey Davy establishes the geometrical and thermal effects of resistance.

_ 1826 A.D. Ohm develops the relationship between potential, resistance, and current.

_ 1837 A.D. Michael Faraday discovers the concept of dielectric constants in materials.

_ 1841 A.D. James Prescott Joule shows relationship of electrical current and thermal heating.

_ 1848 A.D. Gustav Kirchhoff extends the concept of Ohm's law.

_ 1873 A.D. James Clerk Maxwell publishes the work Treatise of Electricity and Magnetism.

_ 1889 A.D. Paschen establishes a relationship explaining the electrical breakdown of gases.

_ 1906 A.D. Toepler establishes a relationship for arc resistance in a discharge process.

_ 1915 A.D. Townsend explains avalanche phenomena in materials.

1.2 Electrostatic Discharge

In the field of ESD, accomplishments to advance the field of electrostatic discharge phenomena are in the form of development of experimental discovery, analytical models, introduction of new semiconductor devices and circuits, test equipment, as well as the development of ESD standards. Below is a short chronological list of key events that moved the field of ESD:

_ 1968 A.D. D. Wunsch and R. R. Bell introduces the power-to-failure electro-thermal model in the thermal diffusion time constant regime.

_ 1970 A.D. D. Tasca develops the power-to-failure electro-thermal model in the adiabatic and steady-state time constant regime.

_ 1971 A.D. Vlasov and Sinkevitch develops a physical model for electro-thermal failure of semiconductor devices.

_ 1972 A.D. W. D. Brown evaluates semiconductor devices under high-amplitude current conditions.

_ 1981 A.D. J. Smith and W. R. Littau develops an electro-thermal model for resistors in the thermal diffusion time regime.

_ 1981 A.D. Enlow, Alexander, Pierce, and Mason addresses the statistical variation of the power-to-failure of bipolar transistors due to semiconductor manufacturing process, and ESD event variations.

_ 1983 A.D. M. Ash evaluates the non-linear nature of the power threshold and the temperature dependence of the physical parameters establishing the Ash relationship.

_ 1983 A.D. V. I. Arkihpov, E. R. Astvatsaturyan, V. I. Godovosyn, and A. I. Rudenko derives the cylindrical nature of the electro-current constriction.

_ 1985 A.D. T. J. Maloney and N. Khurana discusses transmission line pulse TLP) testing as a method for semiconductor I-V characterization and modeling.

_ 1989 A.D. Dwyer, Franklin, and Campbell extends the Wunsch-Bell model to address three-dimensional effects.

_ 1989 A.D. R. Renninger, M. Jon, D. Lin, T. Diep, and T. Welser introduces the first field induced charged device model (CDM) device simulator.

_ 1989 A.D. T. Polgreen and P. Chatterjee explain non-uniform current flow in silicided multi-finger MOSFETs.

_ 1992 A.D. M. Hargrove and S. Voldman quantify CMOS ESD networks in the first CMOS shallow trench isolation (STI) technology.

_ 1992 A.D. S. Voldman discovers the effect of MeV implanted retrograde well dose on ESD robustness.

_ 1993 A.D. D. Lin publishes the first paper on the effect of MOSFET dielectric and junction breakdown scaling on on-chip ESD protection.

_ 1993 A.D. S. Voldman publishes the first paper on the influence on MOSFET constant electric field scaling theory on ESD robustness. A ''Constant ESD scaling'' theory is developed under the constraint of maintaining ESD robustness as technology is scaled.

_ 1993 A.D. ESD Association releases the human body model (HBM) standard for semiconductor component testing.

_ 1993 A.D. H. Geiser introduces the very fast transmission line pulse (VF-TLP) ESD test system.

_ 1994 A.D. A. Ameresekera and C. Duvvury publishes on the influence of MOSFET scaling trends on ESD robustness.

_ 1994 A.D. ESD Association releases the machine model (MM) standard for semiconductor component testing.

_ 1995 A.D. A. Wallash releases the first publication on ESD failure mechanisms in magneto-resistor (MR) recording heads. The significance of the work was the first indication of ESD concerns in the magnetic recording and disk drive industry.

_ 1995 A.D. SEMATECH initiates ESD Working Group to address ESD strategic planning.

The SEMATECH effort addresses ESD technology benchmarking, ESD technology roadmap and test equipment, ESDA and JEDEC ESD specification alignment, and TLP test standard development.

_ 1996 A.D. K. Banerjee develops Ti/Al/Ti interconnect model, extending the work of D. Tasca to modern CMOS interconnects.

_ 1997 A.D. S. Voldman publishes first experimental measurements of ESD in copper (Cu) interconnects, and the comparison to aluminum (Al) interconnects. This work addressesthe influence of CMOS interconnect scaling on ESD robustness, and the evolutionary changes from aluminum to copper interconnects .

_ 1997 A.D. ESD Association Device Testing Standards Committee releases first charged device model (CDM) Standard.

_ 1997 A.D. J. Barth introduces the first commercial transmission line pulse (TLP) device simulator. The introduction of commercial systems has lead to the acceptance of the TLP methodology for ESD sensitivity testing of semiconductors.

_ 1998 A.D. SEMATECH Quality and Reliability ESD Working Group initiates transmission line pulse (TLP) standards effort.

_ 2000 A.D. S. Voldman and P. Juliano published the first ESD measurements in Silicon Germanium (SiGe) technology. The significance of this work is the beginning of the focus of ESD in radio frequency (RF) technology.

_ 2002 A.D. R. Gibson and J. Kinnear initiate the S20.20 ESD Control Certification Program. The significance of this effort is the focus on international certification of ESD control programs.

_ 2003 A.D. Oryx Instruments and Thermo KeyTek, introduces commercial very fast transmission line pulse (VF-TLP) systems. The significance of this work is the introduction of VF-TLP systems as a standard testing methodology for future ESD testing.

_ 2004 A.D. ESD Association Device Testing Standards Committee initiates the trans mission line pulse (TLP) Standard Practice document. The significance of this work is the acceptance of TLP as a standard testing methodology in the semiconductor industry.

1.3 Key ESD Patents, Inventions, and Innovations

In the field of ESD protection, there are many patents, inventions, and innovations that stimulated growth of ESD circuits as well as improved the ESD robustness of circuits themselves. ESD circuit inventions are important in providing innovations and techniques that improve the ESD robustness of semiconductor chips. Interest in ESD patenting of ESD protection networks began in the 1970s, with a continued growth in patent activity, invention, and innovations. Below is a chronological list of key innovations that moved the field of ESD protection forward in the area of ESD circuits. In some cases, no patent for the invention was pursued. Many of the patents chosen in this listing consist of the ESD design practices and subjects and topics which will be discussed in the text.

Starting from the 1970s, here is a listing of key circuit innovations and those which will be referred to in the future Sections:

_ 1970 A.D. M. Fischer (IBM). Resistor-thick oxide FET gate protection device for thin oxide FETs. IBM Technology Disclosure Bulletin 13 (5): 1272-1273. This introduced the use of a gate-coupled ''thick oxide'' field effect transistor and a series resistor element.

This invention discloses the concept of using a thick oxide insulated gate field effect transistor (IGFET) to protect a thin oxide IGFET.

_ 1971 A.D. Boss et al. (IBM). ESD network with capacitor divider and half-pass transmission gate. IBM Technology Disclosure Bulletin. This introduced the concept of using a capacitive divider across a half-pass transmission gate to reduce the gate oxide stress.

_ 1971 A.D. M. Lenzlinger (RCA). ESD distributed diode/resistor double-diode network. RCA Corporation, CD 4013. Publication: ''Gate Protection of MIS Devices'', M. Lenzlinger, IEEE Transactions on Electron Device ED-18 (4): 1971. This publication discloses the concept of a double-diode ESD network as well as a distributed diode resistor transmission line for the diode to VDD.

_ 1973 A.D. G. W. Steudel (RCA). Input transient protection for complimentary field effect transistor integrated circuit device. U.S. Patent No. 3,712,995, January 23, 1973. The patent shows a distributed double-diode ESD network with diode/resistor distributed network, but with the reverse polarity.

_ 1974 A.D. T. Enomoto and H. Morita (Mitsubishi). Semiconductor device. U.S. Patent No. 3,819,952, June 25, 1974. The patent shows the use of a first-stage gate-coupled thick oxide insulated gate field effect transistor (IGFET), a series resistor element (prior to the IGFET drain), and a IGFET source resistor element. This first stage is followed by a second-stage thin oxide IGFET whose gate is coupled to the first-stage IGFET source node. The network introduces the concept of a first- and second-stage ESD network, gate-coupling, series resistor options, as well introduces a de-biasing resistor at the source of the first stage.

_ 1979 A.D. C. Bertin (IBM). Over-voltage protective device and circuits for insulated gate transistors. U.S. Patent No. 4,139,935, February 20, 1979. This patent by Claude Bertin was the first process patent that produced a metallurgical junction with a lower break down voltage using junction ''tailoring'' where the breakdown element was to serve as a ''gate tie down'' or protection network for MOSFET gate oxides.

_ 1983 A.D. N. Sasaki (Fujitsu). Semiconductor integrated circuit device providing a protection circuit. U.S. Patent No. 4,423,431. December 27, 1983. Sasaki introduces the idea of use of a series resistor, and thin oxide transistor as a protection network. The network also introduces gate-coupled thin oxide and a resistor in series with the capacitor.

This is the first network that is using gate-coupled thin oxide devices with a resistor on the gate electrode to ground, in a single-stage implementation.

_ 1983 A.D. L. Avery (RCA). Integrated circuit protection device. U.S. Patent No. 4,400,711. August 23, 1983. This patent used a MOSFET in the regenerative feedback loop of a pnpn silicon-controlled rectifier (SCR) for ESD protection applications.

_ 1989 A.D. C. Duvvury and R. Rountree ( Texas Instruments). Output buffer with improved ESD protection. U.S. Patent No. 4,855,620, August 8, 1989. This patent is the first patent to discuss the optimization of output buffers for ESD protection improvements.

_ 1990 A.D. R. Rountree ( Texas Instruments). Circuit structure with enhanced electrostatic discharge protection. U.S. Patent No. 4,939,616, July 3, 1990. This patent discusses the formation of a low-voltage trigger pnpn silicon-controlled rectifier (SCR) using an n+ diffusion that extends outside of the n-well region to form a lower breakdown voltage and lateral npn element. This innovation was important to produce low-voltage trigger SCRs as technology began to scale.

_ 1992 A.D. A. Graham (Gazelle). Structure for providing electrostatic discharge protection. U.S. Patent No. 5,124,877, June 23, 1992. This patent introduces the concept of a diode string as well as a ''ESD discharge reference rail.'' Today, ESD diode strings are commonly used, as well as the discharge rail concept.

_ 1993 A.D. W. Miller (National Semiconductor). Electrostatic discharge detection and clamp control circuit. U.S. Patent No. 5,255,146, October 19, 1993. This patent was the first patent RC-triggered ESD power clamp network to address the presence of ''detection circuits'' which respond to the ESD pulse. This is the first patent that addresses the usage of an RC network which is chosen to be responsive to the ESD pulse network.

_ 1993 A.D. R. Merrill (National Semiconductor). Electrostatic discharge protection for integrated circuits. U.S. Patent No. 5,239,440, August 24, 1993. This innovation utilized the RC-discriminator network, inverter logic, and logic circuitry that is parallel to the pre drive circuitry, and turns on the I/O off-chip driver (OCD) output stage during ESD events.

_ 1993 A.D. Kirsch, G. Gerosa, and S. Voldman (Motorola and IBM). Snubber-clamped ESD diode string network. This network introduced a diode string as a mixed-voltage interface network and solved the reverse-Darlington amplification using a ''Snubber'' diode element. Implemented into the PowerPC microprocessor and embedded controller family. This was applied to advanced microprocessors for mixed-voltage applications.

_ 1994 A.D. D. Puar (Cirrus Logic). Shunt circuit for electrostatic discharge protection. U.S. Patent No. 5,287,241, February 15, 1994. This introduced the first RC-triggered p-channel MOSFET-based ESD power clamp network.

_ 1994 A.D. J. Pianka (AT&T). ESD protection of output buffers. U.S. Patent No. 5,345,357, September 6, 1994. Development of RC-trigger and gate coupling circuit elements for activation of the output of an n-channel MOSFET pull-up and pull-down off chip driver (OCD). This ESD technique is especially valuable for small computer system interface (SCSI) chips, since only n-channel output transistors are used as the pull-up and pull-down elements.

_ 1996 A.D. T. J. Maloney (Intel). Electrostatic discharge protection circuits using biased and terminated PNP transistor chains. U.S. Patent No. 5,530,612, June 25, 1996.

Maloney's patent application was a second ESD circuit application to address the leakage amplification in diode string ESD networks. This was applied to advanced microprocessors for mixed-voltage applications.

_ 1997 A.D. S. Voldman, S. Geissler, and E. Nowak (IBM). Semiconductor diode with silicide films and trench isolation. U.S. Patent No. 5,629,544, May 13, 1997. This is the first patent that addresses four items: first, it addresses ESD diode structures constructed in shallow trench isolation; second, it addresses STI pull-down effects; it addresses the lateral polysilicon-bound gated ESD p-n diodes; and fourth, the silicon-on-insulator (SOI) lateral ESD gated diode structures.

_ 1997 A.D. D. Krakauer, K. Mistry, S. Butler, and H. Partovi, (Digital Corp). Self referencing modulation circuit for CMOS integrated circuit electrostatic discharge protection clamps. U.S. Patent No. 5,617,283, April 1, 1997. This was the first ESD application using MOSFETs to establish a MOSFET gate-modulation network. This was applied to microprocessor applications.

_ 1997 A.D. S. Voldman (IBM). Power sequence-independent electrostatic discharge protection circuits. U.S. Patent No. 5,610,791, March 11, 1997. This patent is the first patent to address sequencing issues in a multiple-rail power supply chip. The ESD protection circuitry is power sequence-independent thereby eliminating any restrictions on the sequencing of power as applied to, and removed from, the different power supply rails of the IC chip.

_ 1997 A.D. S. Voldman (IBM). Voltage regulator bypass circuit. U.S. Patent No. 5,625,280, April 29, 1997. This patent was the first to address ESD implementations for ESD protection of voltage regulators which are integrated between peripheral I/O and core power rails. This was important for DRAM, SRAM, and ASIC applications with core regulation, mixed-voltage power, and low-voltage core voltages.

_ 1998 A.D. F. Assaderaghi, L. Hsu, J. Mandelman, G. Shahidi, and S. Voldman (IBM).

Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications. U.S. Patent No. 5,811,857, September 22, 1998. This invention discusses the first body- and gate-coupled silicon on insulator (SOI) ESD network applying dynamic threshold MOS (DTMOS) concepts to ESD networks.

_ 1999 A.D. J. Chen, L. Li, T. Vrotsos, and C. Duvvury. PNP-driven NMOS ESD protection circuits. U.S. Patent No. 5,982,217, November 9, 1999. This circuit innovation uses a pnp element to improve the ESD robustness of a MOSFET ESD device. The emitter of a pnp transistor and the drain of protection NMOS device are connected to an I/O pad. The collector of the pnp transistor and the gate of the protection NMOS transistor are connected to ground through a resistor.

_ 1999 A.D. S. Voldman (IBM). Modified keeper half-latch receiver circuit. U.S. Patent No. 5,894,230, April 13, 1999. This patent addressed ESD issues with CMOS receiver circuits which utilized p-channel MOSFET feedback networks, which demonstrated ESD problems in VDD reference test modes. This was very important in achieving ESD robustness in receiver networks for applications below 0.5-mm CMOS technologies.

This network was implemented into CMOS microprocessors, CMOS logic, memory, and ASIC applications.

_ 1999 A.D. S. Voldman (IBM). Electrostatic discharge protection circuits for mixed voltage interface and multi-rail disconnected power grid applications. U.S. Patent No. 5,945,713, August 31, 1999. This patent addresses two concepts: the first concept is for an ESD diode network for a multiple power supplies and separated ground rails, as well as a second circuit is a self-bias well sequence-independent input node ESD circuit. The first network was integrated into CMOS DRAM designs, and the second ESD network was implemented into both CMOS microprocessors, servers, and ASIC I/O libraries. The self bias well sequence-independent circuit was implemented into sequence-independent I/O libraries, which required the ability to lower the power supply voltage when the input pins are positive.

_ 2000 A.D. M. D. Ker (ITRI, Taiwan). Substrate-triggering electrostatic discharge protection circuit for deep-submicron integrated circuits. U.S. Patent No. 6,072,219, June 6, 2000. The patent is the first patent to address substrate triggered ESD protection networks.

_ 2000 A.D. S. Voldman and D. Hui (IBM). Switchable active clamp network. U.S. Patent No. 6,075,399, June 13, 2000. This application demonstrates the first ''active clamp'' network that is suitable for ESD protection in triple well and silicon-on-insulator (SOI) technology that utilizes body-coupling techniques.

_ 2001 A.D. R. Mashak, R. Williams, D. Hui, and S. Voldman (IBM). Active clamp network for multiple voltages. U.S. Patent No. 6,229,372, May 8, 2001. This invention is the first active clamp network used to provide active clamping and ESD protection that utilizes MOSFET body-coupling techniques in a multiple-voltage power supply environments.

_ 2002 A.D. S. Voldman and S. Ames (IBM). Modified current mirror circuit for BiCMOS applications. U.S. Patent No. 6,404,275, June 11, 2002. The invention is the first to address the problem of current mirror circuits on input pads, and develops new current mirror circuits to improve the ESD robustness.

_ 2003 A.D. M. D. Ker, K. K. Hung, and T. H. Tang (UMC). Silicon-on-insulator diodes and ESD protection circuits. U.S. Patent No. 6,649, 944, November 18, 2003. This is the first patent of an SOI ESD lateral gated diode p + /p - /n - /n+ network which uses both well implants, and removes the gate structure for improved ESD protection levels.

_ 2003 A.D. S. Voldman, A. Botula, and D. Hui. Electrostatic discharge power clamp circuit. U.S. Patent No. 6,549,061, April 15, 2003. This is the first silicon germanium (SiGe) ESD power clamp network for mixed-voltage and mixed-signal applications using high frequency, and high-breakdown SiGe HBT devices. The significance of the invention is the utilization of the natural scaling of the breakdown voltages of a SiGe HBT device.

_ 2003 A.D. S. Voldman. SOI voltage-tolerant body-coupled pass transistors. U.S. Patent No. 6,628,159, September 30, 2003. This patent is the first patent to address the ESD failure mechanisms of a SOI half-pass transmission gate (e.g., pass transistor) using body coupling techniques.

_ 2003 A.D. K. Verhaege, M. Mergens, C. Russ, J. Armer, and P. Jozwiak. Multi-finger current ballasting ESD protection circuit and interleaved ballasting for ESD sensitive circuits. U.S. Patent No. 6,583,972, June 24, 2003. This patent addresses the concept of using gate-coupling from one MOSFET finger to another in a ''domino'' fashion.

1.4 Table of ESD Defect Mechanisms

TABLE1 ESD failure mechanisms in CMOS semiconductor devices

TABLE2 ESD failure mechanisms in silicon-on-insulator (SOI) technology

TABLE3 ESD failure mechanisms of silicon, silicon germanium, and silicon germanium carbon bipolar elements

Semiconductor device and circuit failure occurs from both electro-thermal or electrical breakdown mechanisms. The ESD failure mechanisms will be a function of the technology type, semiconductor device type, the ESD event type, the polarity of the ESD event, and the grounded reference source. In TABLE1, examples of ESD failure mechanisms are shown for bulk CMOS semiconductor device elements whether used in ESD networks or circuits.

In a silicon-on-insulator (SOI) technology, ESD failure mechanisms can be significantly different than those observed in bulk CMOS. The substrate region is physically separated from the semiconductor devices using a buried oxide (BOX) region. The existence of the BOX region changes the failure modes and mechanisms significantly. TABLE2 shows SOI ESD failure mechanisms.

In TABLE3, ESD failure mechanisms in bipolar technology are shown. In bipolar technology, and in bipolar complimentary MOS (BiCMOS), the bipolar emitter base region is the most sensitive structural feature of the bipolar transistor. Low-level ESD failures typically occur in the emitter-base junction due to thermal second breakdown. Additionally, bipolar collector-to-emitter, base-to-collector, and collector-to-substrate failures can occur but at higher voltage conditions.

TABLE4 ESD failure mechanisms in Passive elements

TABLE5 ESD failures in gallium arsenide elements

Passive elements used in CMOS, RF CMOS, BiCMOS, and RF BiCMOS include base- collector junction varactors, hyper-abrupt junction varactors, metal-insulator-metal (MIM) capacitors, and inductors. Passive elements can undergo ESD failure depending on the location within the circuit or chip. Passive elements can serve as ESD elements or circuit network elements. TABLE4 shows a listing of ESD failure mechanisms.

TABLE5 shows a listing of ESD failure mechanisms in gallium arsenide products. In the table, GaAs MESFET failures are shown. GaAs failure mechanisms occur in the GaAs device, from the physical GaAs films, and the interconnect materials (e.g., AuNiGe films).

GaAs heterojunction bipolar transistors (HBT) are sensitive in the emitter-base region similar to the silicon bipolar transistor. Additionally, passive elements are also vulnerable to ESD events. Below is a list of some GaAs failure mechanisms.

ESD failures occur in structures that are needed for semiconductor chip design. TABLE6 is a summary of the failure mechanisms. ESD failure mechanisms can occur from ''no connect pads,'' floating pads, sense pads, metal bussing, programmable power pads, decoupling capacitors, and other integration elements. TABLE6 provides a list of different type of failure mechanisms that occur in a semiconductor chip.

TABLE7 shows a listing of common circuit elements in CMOS design and BiCMOS design. The listing includes off-chip drivers (OCD), receivers, phase-lock loop, active clamp networks, decoupling capacitors, and other common circuit components. These will be discussed in the text.

TABLE6 ESD failure mechanism in semiconductor chip architecture

TABLE7 ESD failure mechanisms in common circuit networks

2. FUNDAMENTAL CONCEPTS OF ESD DESIGN

2.1 Concepts of ESD Design

Fundamental concepts and objectives exist in the ESD design of semiconductor devices, circuits, and systems. The key questions to ask about ESD design are the following:

_ What is it that makes ESD design unique?

_ How is it distinct from standard circuit design practices?

Another way of stating this is--How is ESD design practices different from all other design practices? A first unique design objective is to prevent any physical element in the system from latent or permanent damage that impacts the functionality, reliability, or quality from ESD events. A corollary to this is to prevent latent or permanent damage below a desired current or voltage magnitude. This is the first objective of ESD design. What else makes ''ESD design'' unique?

Here are some of the distinctions and differences:

_ Device Response to External Events: Design of devices and circuits to respond to (and not to respond to) unique current waveforms (e.g., current magnitude and time constants) associated with external environments.

_ Alternate Current Loops: Establishment of alternative current loops or current paths which activate during high-current or high-voltage events.

_ Switches: Establishment of ''switches'' that initiate during high current or voltage events.

_ Decoupling of Current Paths: Decoupling of sensitive current paths.

_ Decoupling of Feedback Loops: Decouple of loops that initiate pinning during off condition or ESD test modes.

_ Decoupling of Power Rails: Decoupling of electrical connections to grounded references and power supplies.

_ Local and Global Distribution: Local and global distribution of electrical and thermal phenomena in devices, circuits, and systems.

_ Usage of Parasitic Elements: Utilization and avoidance of parasitic element in the design practice.

_ Buffering: Utilization of current and voltage buffering of sensitive devices, circuits, or sub-circuits.

_ Ballasting: Introduction of resistance to redistribute current within a single element or a plurality of elements.

_ Unused Sections of a Semiconductor Device, Circuit or Chip Function: Utilize ''unused'' segments of a semiconductor device for ESD protection, which was not utilized for functional applications.

_ Impedance Matching between Floating and Non-Floating Networks: Matching of conditions during testing to allow matching between networks.

_ Unconnected Structures: Addressing structures not containing electrical connections to the power grid or circuitry.

_ Utilization of ''Dummy Structures and Dummy Circuits'': Use of ''dummy structures'' as a means to provide linewidth matching.

_ Non-scalable Source: The ESD event does not scale, while the devices are scaled each technology generation.

_ Area Efficiency: Focus on area efficiency to utilize all of the physical device area for ESD protection.

2.2 Device Response to External Events

On the first issue of preventing any physical element in the system from latent or permanent damage that impacts the functionality, reliability, or quality from ESD events, there is significant misunderstanding. It is a belief of many engineers that the objective of the ESD networks is to carry all of the ESD current, as well as be the first element to undergo failure.

It is also a belief that it does not matter if the ESD structure undergoes failure. These statements are not accurate understanding of the objective of ESD design. The role of the ESD network is to increase the ESD robustness of the complete product or application. The ''failure criteria'' is based on the functional, reliability, or quality objective of the electrical component.

In ESD design, the ESD devices as well as the circuits which are to be protected can be designed to respond to (and not to respond to) unique ESD current waveforms. In standard circuit design, digital circuits are designed to switch from logic state levels, rising or falling edges. Circuits can store information or mix different logical states. ESD networks typically are designed to respond to specific ESD pulses. These networks are unique in that they address the current magnitude, frequency, polarity, and location of the ESD events. Hence, in ESD design, the ESD networks are designed and tuned to respond to the various ESD events.

In ESD design, different stages or segments of the network can also be designed to respond to different events. For example, some stages of a network can respond to human body model (HBM) and machine model (MM) events, while other segments respond to the charged device model (CDM) event. These ESD events differ in current magnitude, polarity, time constant, as well as the location of the current source. Hence, the ESD circuit is optimized to respond and address different aspects of ESD events that circuits may be subjected to. Additionally, circuits can be modified to be less sensitive to ESD events using ESD circuit techniques. As a result, the understanding of the material, device, circuit, and system physical time constants is critical in ESD design.

2.3 Alternate Current Loops

A unique issue is the establishment of alternative current loops or current paths which activate during high current or voltage events. By establishing alternative current loops, or secondary paths, the ESD current can be redirected to prevent over-voltage of sensitive circuits. In peripheral circuit design, this concept is used for overshoot and undershoot phenomenon. In peripheral circuit design, both passive and active ''clamping'' is used to eliminate over-voltage of circuit networks; this practice is most akin to the ESD methodology. As a result, in order to have an effective ESD design strategy, this current loop must respond to the ESD event and have a low impedance. A distinction from peripheral circuit methodology of clamping is the current magnitude; ESD events have significantly higher currents than the overshoot and undershoot phenomenon experienced in peripheral circuit design. Hence, the ''ESD current loop'' must achieve a similar objective, but must have lower impedance.

2.4 Switches

On the issue of establishment of ''switches'' that initiate during high current or voltage events, the uniqueness factor is that these are at time either passive or activated by the ESD event itself. A unique feature of ESD design is that it must be active during unpowered states. Whereas in peripheral circuit design, passive and active clamps are typically utilized in powered states. Hence, the ''switches'' used to sway the current into the ESD current loop are initiated passively, or are initiated by the ESD event itself. Hence, the ESD event serves as the current and voltage source to initiate the circuit. These switches lead to ''current robbing'' and the transfer of the majority of the current from the sensitive circuit to the alternative current loop. Although today there is some interest in ESD design in powered states, the majority of testing, and design practices assume an unpowered design. As a result, the ESD design must use ''switches'' or ''triggers'' that initiate passively (e.g., a diode element), or actively (e.g., a frequency-triggered ESD network). A design objective is to provide the lowest voltage trigger allowable in the application space. Hence, a key ESD design objective is to utilize low-voltage trigger elements that serve as a means to transfer the current away from the sensitive circuit to alternative current paths. A large part of effective ESD design is the construction of these switches or trigger elements.

2.5 Decoupling of Current Paths

An additional design method is the decoupling of elements in the ESD current path. Circuit elements can be introduced which lead to the avoidance of current flow to those physical elements. The addition of ''ESD decoupling switches'' can be used to decouple sensitive circuits as well to avoid the current flow to these networks or sections of a semiconductor chip. ESD decoupling elements can be used to allow elements to undergo open or floating states during ESD events. This can be achieved within the ESD network, or within the architecture of a semiconductor chip.

Decoupling of sensitive elements or decoupling of current loops can be initiated by the addition of elements that allow the current loop to ''open'' during ESD events. During ESD testing, power rails and ground rails are set as references. The decoupling of nodes, elements, or current loops relative to the grounded reference prevents over-voltage states in devices, and eliminates current paths. These decoupling elements can avoid ''pinning'' of electrical nodes. Hence, integration of devices, circuits elements, or circuit function that introduce decoupling electrical connections to ground references and power supplies references, is a key unique ESD design practice.

2.6 Decoupling of Feedback Loops

Feedback loops can lead to unique ESD failures and lower ESD results significantly. The decoupling of nodes, elements, or current loops relative to the grounded reference prevents over-voltage states in devices, and eliminates current paths initiated by the feedback elements. These decoupling elements can avoid ''pinning'' of electrical nodes. Hence, integration of devices, circuits elements, or circuit function that introduce decoupling electrical connections to ground references, and power supplies references of the feedback elements during ESD testing is also a key unique ESD design practice.

2.7 Decoupling of Power Rails

Electrical coupling of sensitive nodes to the power supply rails can lead to ESD failure. The electrical coupling of nodes to the power supply rails, ground rails or chip substrate can lead to ESD failure. Semiconductor elements whose nodes are connected to the power supply can establish current paths, constrain electrical potential, establish ''pinning'' of nodes and circuits, or undergo electrical overstress. A key ESD design practice is establishing methods to electrically decouple from power rails to avoid electrical overstress of electrical nodes and components, as well as eliminate undesirable current paths.

2.8 Local and Global Distribution

To provide an effective ESD design strategy, the ESD design practices must focus on the local and global distribution of electrical and thermal phenomena in devices, circuits, and systems. Locally, good current distribution lowers the current density in physical elements.

As the current distribution improves, the local self-heating can be reduced; this increases the margin to thermal breakdown. As the current distributes, the effectiveness of the device helps improving the utilization of the total area of the ESD network or circuit element. On a circuit and system level, the distribution of the ESD current within the network or system, lowers the effective impedance, and lowers the voltage condition within the ESD current loop. The ESD events are transient events; the physical time constants of the devices, circuits, and system are critical in the understanding, modeling, and simulation of the effectiveness of the elements in the system. A key design practice of ESD devices and circuits is the desire to distribute the current to provide improved design utilization to achieve higher ESD robustness.

2.9 Usage of Parasitic Elements

ESD networks are concerned with parasitic devices inherent in the standard devices, or exist between adjacent structures or devices. ESD design either utilizes or avoids activation of these parasitic elements in the ESD implementations. Utilization of parasitic elements is a common ESD design practice for ESD operation. For example, MOSFET structures in wells form parasitic lateral or vertical bipolar transistors with their corresponding wells or substrate regions. Diodes in the substrate can also form lateral bipolar devices with adjacent well regions or devices. Diodes within isolation regions, such as a well, dual-well, or triple-well isolation, can utilize the parasitic elements for the ESD protection scheme. These can include both vertical and lateral parasitic elements inherently within the standard devices and within the technology. It is not common to use these parasitic elements in standard circuit design, whereas for ESD design it is very prevalent to utilize the parasitic devices and is part of the ESD design practice and art.

2.10 Buffering

In ESD design, it is also a common practice to establish current and voltage buffering of sensitive devices, circuits, sub-circuits, chip level core regions, or voltage islands. This can also be done to provide isolation between radio frequency (RF), analog, and digital segments of a semiconductor chip. A design practice is to increase the impedance in the path of the sensitive circuit either by placement of high-impedance elements, establishing ''off'' states of elements, voltage and current dividing networks, resistor ballasting, or initiating elements in high-impedance states.

2.11 Ballasting

Resistive, capacitive, or inductive ballasting can be introduced to redistribute current or voltage within a single element or a plurality of elements, circuit, or chip segment. The usage within a semiconductor device element allows for redistribution within a device to avoid electro-thermal current constriction, and poor area utilization of a protection network or circuit element. The usage of ballasting allows to redistribute the source current from the ESD event to avoid thermal heating or electrical overstress within the semiconductor network or chip. Ballasting can be introduced into semiconductor device structures using the following ESD design methods:

_ Semiconductor process implant design choices (e.g., sheet resistance, profile, dose, and energy).

_ Semiconductor material choice (e.g., titanium vs. cobalt).

_ Use of multiple material phase states (e.g., C49 and C54 titanium phase states).

_ Silicide removal in the direction of current flow.

_ Silicide removal lateral to the direction of current flow.

_ Introduction of resistor elements (e.g., n-diffusion, p-diffusion, n-well, polysilicon film, tungsten local interconnect, and wire resistors).

_ Introduction of elements with positive or negative temperature coefficient of resistance (TCR).

_ Segmentation by introduction of isolation regions.

_ Segmentation by introduction of lateral high-resistance regions in the semiconductor device.

_ Segmentation by introduction of high-resistance regions in the well or substrate regions.

2.12 Unused Sections of a Semiconductor Device, Circuit, or Chip Function

In ESD design, it is common to utilize ''unused'' segments of a semiconductor device for ESD protection, which was not utilized for functional applications. For example, in a ''gate array'' design practice, elements are not connected for functional usage. An ESD design practice is to use them for ESD protection purposes.

2.13 Impedance Matching Between Floating and Non-Floating Networks

In ESD design, it is common to utilize the ''unused'' segments of a semiconductor device for ESD protection and impedance match the network segments for ESD operation; this matching of conditions during ESD testing allows for current sharing during matching between networks and common triggering voltage conditions.

2.14 Unconnected Structures

In semiconductor chips, there are many structures which are electrically not connected to other circuitry or power grids which are vulnerable to ESD damage. In functional designs, these are not a concern. But in ESD design practice, these unconnected structures are locations of potential charging and dielectric breakdown. Hence in ESD design, unique solutions are required.

2.15 Utilization of Dummy Structures and Dummy Circuits

In the ESD design practice it is not uncommon to utilize dummy structures or dummy circuits which serve the purpose to provide better current uniformity or distribution effects; this concepts span from usage of dummy MOSFET polysilicon gate fingers to dummy inverter circuits.

2.16 Non-Scalable Source Events

Another key issue is that the ESD event is a non-scalable event. Each generation, the size of devices are scaled to smaller dimensions. The ESD design practice must address the constant source input current and the physical scaling of the structures. A unique ESD scaling theory and strategy must be initiated to address this issue.

2.17 Area Efficiency

As in power electronic applications, the area of efficiency of a device, or network for redistribution of the ESD current is a key ESD design metric. Area efficiency of a device, network, or chip is important issue in ESD design.

3. TIME CONSTANTS

Time is an important variable in the understanding of ESD phenomena and ESD design.

Time influences the physical phenomenon that is involved, the response of the material, and the response of the semiconductor device, circuit, or chip to the time-dependent ESD phenomena. Time affects the range of the distribution and propagation of the signal, and its distribution through the physical system. Given a physical system, a characteristic length and a characteristic time can be established to explain a physical system. Hence, it is important to understand the time scales, and time constants to comprehend the interaction. As a result, a time constant approach is chosen as a way to introduce the subject of ESD phenomena.

3.1 Characteristic Times

3.2 Electrostatic and Magnetostatic Time Constants

Given a physical system, a characteristic length and a characteristic time can be established to explain a physical system. Let us define a scale of characteristic length l and characteristic dynamical time _. Electrical phenomenon involves both electrical and magnetic fields. The electric and magnetic fields are coupled through Maxwell's equations. Three important time constants allow us to understand the validity of the electrical phenomenon. The three physical time constants of interest are the charge relaxation time, _e, the magnetic diffusion time, _m, and the electromagnetic wave transit time, _em.

3.2.1 Charge relaxation time

Let us define the charge relaxation time, _e

The charge relaxation time is the physical RC time of the medium. It determines how fast a medium responds to an electrical transient state. For example, it determines how well a material screens an electric field from within a medium. This is more apparent when the physical dimensions are added to the time constant.

3.2.2 Magnetic diffusion time

The magnetic diffusion time, _m, is ...

The magnetic diffusion time is the L/R time of the medium. This is a time constant associated with how a medium responds to a magnetic transient state. This is more apparent when put in the following form,

Electromagnetic wave transit time The electromagnetic wave transit time, _em, is the time it takes for an electromagnetic plane wave to propagate a distance l

_em = l c where c is the speed of light in a medium. The speed of light in a medium can be expressed as c = 1

_" p From this we can express the electromagnetic transit time as

__ r The electromagnetic transit time, _em , can then be expressed as,

FIG. 1 Electro-quasistatic time constant hierarchy

In this form, the electromagnetic transit time is the arithmetic mean of the magnetic diffusion time and the charge relaxation time. Note that putting in the macroscopic dimensions, we can express this as

In this form, the electromagnetic wave transit time is the square root of the inductance and the capacitance.

Let us define an additional parameter _

_ where the parameter is the ratio of the electromagnetic transit time to the characteristic time. For Maxwell's equations to reduce to the electro-quasistatic (EQS) assumption, the magnetic diffusion time must be less than the charge relaxation time and the characteristic time _ must be much greater than the electromagnetic transit time. FIG. 1 shows the electro-quasistatic time constant hierarchy.

In the majority of ESD concerns which is of interest in the scope of the text, electrostatics and electro-quasistatics are valid. The characteristic time scale of an ESD pulse will be of the order of a nanosecond to tens of nanoseconds, which is significantly longer than the electromagnetic transit time of a semiconductor device, circuit, or chip. For semiconductor, the substrate materials are such that the charge relaxation time is longer than the magnetic diffusion time as a result of the magnetic permittivity values and electrical permittivity. As the analysis addresses electrical interconnects, packaging, and transmission line pulse systems, the characteristic time approaches the electromagnetic transit time. In the analysis of ESD events involving the arc discharge, both current phenomena and electromagnetic emissions are present of a TE, TM, and TEM form.

For Maxwell's equations to reduce to the magneto-quasistatic (MQS) assumption, the charge relaxation time must be less than the magnetic diffusion time and the characteristic time _ must be much greater than the electromagnetic transit time. In most ESD problems, the analysis does not involve the MQS analysis. But, there are some cases, such as magnetic recording media, magnetic memory, and MRAMs, where the MQS assumption is valid.

3.3 Thermal Time Constants

ESD phenomena is both electrical and thermal in nature. The time regimes of thermal analysis is divided into three regimes, based on the thermal diffusion time. These regimes are known as the adiabatic time regime, the thermal diffusion time regime, and the steady-state regime. These regimes directly follow from the assumption of the relative time scales compared to the thermal diffusion; this directly follows from the solution of the partial differential equation known as the thermal diffusion equation.

3.3.1 Heat capacity

Heat capacity of a medium is the ability of a medium to store energy. The heat capacity of the system is expressed as the product of the mass density, _, the specific heat, cp, and temperature

3.3.2 Thermal diffusion

Thermal transport occurs as a result of a gradient in the temperature field. Thermal conduction occurs as a result of thermal diffusion.

3.3.3 Heat transport equation

ESD phenomena involves both electrical and thermal phenomena. The temperature field in a medium can be determined from the differential equation of heat conduction. The temperature at any point in the medium can be quantified by understanding the energy balance in a given region. The energy-balance equation for an infinitesimal volume is determined by the sum of the net rate of heat entering the volume, and the rate of energy generation in the volume, which is equal to the rate of increase of the internal energy in the volume. The net rate of heat entering the infinitesimal volume is equal to the heat flowing into the volume and the heat flowing out of the volume. The sum of the differential heat flow in all directions determines the net rate of heating in the volume. This term is the divergence of the heat flux. The rate of energy generation in the volume is associated with the generation sources in the infinitesimal. The rate of increase in the internal energy is associated with the increase in the heat capacity of the system. The energy balance equation in this form is also known as the heat equation, or the partial differential equation of heat conduction,

In the case that the thermal conductivity, k, is position and temperature independent, the thermal conductivity variable can be separated from the heat flux term. In this case, the partial differential equation of heat conduction can be normalized. The heat flux term can be simplified as the Laplacian of temperature and expressed as ...

In this form, the thermal diffusivity is defined as ...

This equation in this form is important for quantifying the ESD event in the location where the heat generation is occurring. This is typically in the region of electrical current fluence or electrical current generation. For example, heat is generated in the source, drain, and channel of a MOSFET as a result of Joule heating.

Given that there is no internal generation of heat sources inside the medium, the partial differential equation of heat conduction can be simplified to the Fourier equation, also known as the diffusion equation.

The Fourier equation is also known as the parabolic equation since it is a differential equation which is first order in time and second order in space. For ESD analysis, this equation is applied in regions where there are no sources of thermal generation, yet whose temperature field is being influenced by heat flux or temperature gradients inside the regions or on its boundaries.

For steady-state processes, the partial differential equation of heat conduction simplifies to...

For the case of a uniform thermal conductivity (space and time), the partial differential equation of heat conduction reduces to the Poisson equation with temperature as the field variable. The Poisson equation is valuable for analysis of self-heating processes which are steady state. In the case that there is no internal generation, uniform thermal conductivity, and no heat generation, the Poisson equation simplifies to the Laplace equation r2 T = 0 1.3.4 Thermal Physics Time Constants From the partial differential equation of heat conduction, a characteristic time associated with thermal diffusion is the thermal diffusion time, _T,

...where...

...is the thermal diffusivity,

= k=_cp and l is the characteristic length. Given an oscillatory steady-state thermal excitation which has an angular frequency, omega , where the spatial wavelength is much shorter than other physical characteristic lengths, a thermal skin depth can be defined as ...

3.4.1 Adiabatic, thermal diffusion time scale and steady state

FIG. 2 Electro-quasistatic and thermal time constant hierarchy

ESD phenomenon in semiconductors concerns itself with events where the time scale of the applied pulse and response of the medium, circuit, and systems are of primary interest.

The hierarchy of characteristic times must be established to understand the physical phenomenon and the relationship of the ESD event characteristic times. The characteristic time of the ESD event relative to the electromagnetic wave transit time, the charge relaxation time, the magnetic diffusion time, and the thermal diffusion time are important to understand the physical response.

In semiconductors such as silicon, the hierarchy of characteristic times follow the EQS assumption. FIG. 2 shows the electro-quasistatic and thermal time constant hierarchy.

For an EQS assumption, the magnetic diffusion time is shorter than the electromagnetic transit time. The ordering of characteristic times are the magnetic diffusion time, the electromagnetic transit time, and then the charge relaxation time. Additionally, the time region of interest is such that the electromagnetic transit time is significantly smaller than the characteristic time of the pulse (e.g., 1). The ordering of these characteristic times must be true to insure validity of the EQS assumption. To address the issue of thermal transport, there are three regions of interest within this hierarchy of characteristic times. When the characteristic pulse time, _, is much shorter than the thermal diffusion time, the thermal transport due to conduction is negligent. This is the ''adiabatic assumption.'' As the characteristic pulse time, _, is of the same order of magnitude as the thermal diffusion time, the hierarchy of the time scales is such that _ ~ O. This will be referred to as the

''thermal diffusion regime assumption.'' As the characteristic pulse time is significantly longer than the thermal diffusion time, the solution approaches a steady-state response known as the ''steady-state assumption.''

3.5 Semiconductor Device Time Constants

3.5.1 Depletion region transit time

For the diode depletion region transit time, the time it takes to traverse the depletion width is a width of the depletion region divided by the drift velocity of the carrier,

_t = Wd vd

where the depletion width can be expressed as a function of the doping concentration on both sides of the metallurgical junction,

1 2 and the drift velocity can be expressed as the product of the mobility times the peak electric ...

field, vd = _jEj

The peak electric field in the junction can be expressed as a function of the voltage across the depletion region, and the doping concentrations, Epeak

This time constant is important in that it is a key time constant when a diode element is used as an ESD element, or a switching element. This is of greater concern in addressing high-speed ESD phenomena such as the charged device model (CDM) events.

3.5.2 Silicon diode storage delay time

In the switching of a silicon diode, stored charge in the base region can limit the diode speed.

The diode storage delay time can be expressed as, ...

which is the product of the recombination time of a p+n diode, and the inverse error function of the ratio of the forward and reverse currents. Note that this time constant is a function of the current in a semiconductor device, and can be limiting during fast ESD events.

3.5.3 Bipolar base transit time

The bipolar base transit time is the time for a carrier to diffuse across the base region. This is equal to the base width divided by the diffusion velocity; this can be expressed as a function of the base width and the diffusion coefficient,

...where WB is the base width, and D is the diffusion coefficient. This time constant is important for the understanding of the time response of a bipolar transistor.

3.5.4 Bipolar turn-on transient time

For the turn-on transient of a bipolar transistor, the time constant is a function of the recombination time, the base current, and collector current ...

3.5.5 Bipolar turn-off transient time

For the turn-off transient time of a bipolar transistor, the time constant is a function of the recombination time, the base current, and collector current.

3.5.6 Bipolar emitter transition capacitance charging time

In a bipolar transistor, there is a finite ''RC'' time for the response of the emitter. The response of the emitter is a function of the emitter resistance, rE, and the associated emitter capacitance at zero bias voltage …with emitter resistance equal to the thermal voltage divided by the emitter current

rE = kT qIE

...and the capacitance is the dielectric constant divided by the depletion width (at zero volts) CTE

3.5.7 Bipolar collector capacitance charging time

The bipolar collector capacitance charging time is analogously similar to the emitter capacitance charging time. The bipolar collector charging time is associated with the collector resistance (e.g., sub-collector resistance) and the collector capacitance. This can be expressed as ...

3.5.8 Silicon controlled rectifier (SCR) time response

Silicon controlled rectifiers (SCR) are used as ESD protection circuits on input nodes and power supplies. The time response of the SCR circuit is the sum of the base transit times across the pnp and npn bipolar transistor elements ...

__ 2Dn and for the npn bipolar device, the base transit time is ...

3.5.9 MOSFET transit time

The MOSFET device has characteristic time constants associated with the transport of the carriers from the MOSFET drain to the source. The MOSFET channel transit time is equal to the MOSFET effective channel length, Leff, divided by the carrier drift velocity, vd, in the channel

_t = Leff vd

The carrier drift velocity is equal to the product of the electron mobility and saturation electric field.

vd = _Esat where the saturation electric field, Esat, is equal to the MOSFET source-to-drain voltage divided by the MOSFET effective channel length, Leff. The MOSFET source-to-drain transit time can be expressed as the ...

MOSFET drain charging time

The MOSFET drain charging time is the time it takes to charge up the drain node of a MOSFET. This is important in ESD networks in that for the MOSFET snapback voltage, there is a finite time for the MOSFET drain to rise. The MOSFET drain rise time is equal to the MOSFET drain resistance and the MOSFET drain capacitance. The drain resistance is a function of the MOSFET drain sheet resistance, the MOSFET width, and the number of MOSFET fingers. The MOSFET drain capacitance is a function of the MOSFET channel width, the number of MOSFET fingers, and the MOSFET drain junction capacitance per unit area.

This time constant is important in understanding the drain response during ESD events when a MOSFET structure is used as an ESD element, or in ESD MOSFET drain-coupling networks.

3.5.11 MOSFET gate charging time

The MOSFET gate charging time is the time it takes to charge the MOSFET gate electrode.

This will be a function of the MOSFET gate resistance and the MOSFET gate-to-channel capacitance. The gate resistance is a function of the polysilicon MOSFET gate sheet resistance, the MOSFET channel length, the MOSFET width, and the number of MOSFET fingers.

The MOSFET gate capacitance is a function of the MOSFET channel length, MOSFET channel width, the number of MOSFET fingers, and the gate capacitance per unit area

3.5.12 MOSFET parasitic bipolar response time

During ESD events, the parasitic bipolar transistor plays a role in the response of a MOSFET transistor. The MOSFET bipolar base transit time is the time for a carrier to diffuse across the MOSFET drain to the MOSFET source, in the channel region. This is equal to the MOSFET channel length divided by the diffusion velocity in the MOSFET channel region;

this can be expressed as a function of the MOSFET channel length, Leff, and the diffusion coefficient, D, in the MOSFET channel region

This time constant is important in the understanding of the response of a MOSFET during fast ESD events.

3.6 Circuit Time Constants

3.6.1 Pad capacitance

In the analysis of the ESD response, the capacitance of the pad acts as a load in the ESD analysis. The pad capacitance influences the RC time of the network Cload = Cpad

3.6.2 Half-pass transmission gates (TG)

The understanding of the time delays of the half-pass transmission gates is key to the response to receiver networks. Additionally, the time delays are also associated with the CMOS inverter propagation delay times.

3.6.3 n-Channel half-pass transistor charging time constant

The time delay in charging a output capacitance load, Cout, with a transmission gate voltage equal to VDD, has a n-channel half-pass transmission gate charging time of ...

...where the output voltage through the half-pass transmission gate can be expressed as ...

3.6.4 Half-pass transistor transmission gate discharge time constant

The half-pass transistor transmission gate discharge time constant to pass a logical ''0'' has a discharge time constant equal to ...

...where the voltage at the output of the half-pass transistor has the form ...

3.6.5 p-Channel half-pass transistor charging time constant

For the case of the p-channel half-pass transistor transmission gate, the charging and discharging time constants are analogous but opposite in form. For transmission of a logical…

…where…

For transmission of a logical ''0,'' the discharge event can be expressed where the output voltage through the half-pass transmission gate can be expressed as …

3.6.6 Inverter propagation delay time constants

The propagation time constants associated with an inverter has the same nature as the time constants associated with the half-pass transmission gates. In an inverter, the charging and discharging of the load occurs through the p-channel MOSFET or the n-channel MOSFET identical to the half-pass transistor.

3.6.7 High-to-low and low-to-high transition time

The high-to-low transition time can be defined as a function of the charging and discharging times of an half-pass transmission gate (V0 is 10% transition point of VDD, or 0.1 VDD)

3.6.8 Inverter propagation delay time

The CMOS inverter propagation delay time can be represented as […]

3.6.9 Series n-channel MOSFETs discharge delay time

Given a set of n-channel transistors in a series configuration, the transistors serve as a series of half-pass transistors. The transistors each have a corresponding diffusion capacitance from the MOSFET source and drain diffusion; each MOSFET channel region serves as the series resistance element. To evaluate the delay time constant for a series-connected MOSFETs this can be treated as a lumped RC transmission line or RC ladder network. A simplified solution for N transistors in a series configuration, the delay time can be estimated as the superposition of time constants […]

For each time constant in the expression, the i th element in the RC ladder network is the product of the i th capacitor element and the summation of all the resistances to the i th element, ...

...where for n-channel MOSFET devices

3.6.10 Series p-channel MOSFETs charge delay time

Given a set of p-channel transistors in a series configuration, the transistors serve as a series of half-pass transistors. The transistors each have a corresponding diffusion capacitance from the MOSFET source and drain diffusion; each MOSFET channel region serves as the series resistance element. As in the n-channel case, to evaluate the delay time constant for a series connected MOSFET, this can be treated as a lumped RC transmission line, or RC ladder network. A simplified solution for N transistors in a series configuration, the delay time can be estimated as the superposition of time constants ...

For each time constant in the expression, the ith element in the RC ladder network is the product of the ith capacitor element and the summation of all the resistances to the ith element

3.7 Chip Level Time Constants

On the semiconductor chip level, the critical chip time constants of interest to ESD protection is the global time constants and the package level time constants:

_ Peripheral I/O power bus time constant.

_ Core chip power grid time constant.

_ Substrate time constant.

_ Package level time constants.

3.7.1 Peripheral I/O power bus time constant

During ESD events, the current flows through the ESD network to the power bus. Along the power bus is a plurality of peripheral circuit books. The peripheral circuits contain pads, ESD networks, and the receiver or transmitter books. The peripheral power bus extends over these circuits in a regular spacing. Hence, we can represent the power bus time constant as a RC ladder network. The incremental resistor element is the bus resistance between adjacent peripheral I/O cells, and the incremental capacitance element is the loading of the individual peripheral circuits books, and the bus capacitance. The incremental bus resistance is ...

where L is the spacing between adjacent I/O cells, Wbus is the bus width. The incremental capacitance is the incremental bus capacitance term and the book capacitance C = Cbus + Cbook and incremental capacitance

Cbus = "eff LWbus d

The number of external pins can be estimated from the number of circuits in the semiconductor chip according to Rent's Rule

Np = KpN g

where Np is the number of external pins, Ng is the number of total gates, and Kp and are proportionality constants. From the knowledge of the chip size and the number of circuits, the number of pins along the bus can be estimated.

3.7.2 Core chip time constant

The response time of the core chip is a function of the total chip capacitance. The chip capacitance is proportional to the number of circuits and the capacitance per internal circuit.

From Rent's Rule, knowing the number of I/O pins, we can estimate the number of internal circuits.

From this expression, knowing a capacitance of a typical inverter circuit, the loading effect on the power grid can be estimated. Assume the loading capacitance of a typical network is Cg , an estimate of the total circuit capacitance loading can be expressed as Cg.

The total chip capacitance can also include the decoupling capacitors that are added to increase the total chip capacitance.

In evaluation of the chip response, the resistance and the capacitance both play a role. The estimate of the resistance is a function of the architecture and chip design methodology. Hence, there is an RC time associated with the chip response.

3.7.3 Substrate time constants

The response of the chip substrate also plays a role in ESD phenomenon. On a global level, the substrate time constant is a function of the substrate resistance and the substrate contact density. From Rent's Rule, we can project the number of substrate contacts in the core of the chip from the knowledge of the internal number of circuits. Knowing the number of internal gates, we can assume that there is a substrate contact for some proportionality constant for every circuit. This is a valid assumption, since for latchup it is required to have a local substrate contact within a given distance from all circuits, assuming some proportionality constant,

Nsx ()Core= Ng

The spacing of the substrate contact relative to the circuit and the size of the average internal circuit will lead to the defining of the proportionality constant. Additionally, for the peripheral circuits, we can assume each I/O circuit has a substrate contact

Nsx ()I=O= KpN g

The incremental resistance between substrate contacts will be a function of the chip area, the contact-to-contact spacings, and the substrate resistance. This network will form a two dimensional resistance grid. Hence the substrate network will primarily be a time constant associated with a resistance network. The resistance distribution will respond as a resistance-conductance (RG) transmission line. For the substrate, the capacitance formed between the substrate and the package has a role in the capacitance coupling during a charged device model (CDM).

3.7.4 Package time constants

In ESD events, packages have an influence on HBM, MM, and CDM events. The package can be modeled as a capacitor-inductor lumped parameter. A typical package model will consist of a _-network, consisting of a first shunt capacitor, a series inductor, and a second shunt capacitor element. In some package designs, the lead frames and wire bond also serve as a series inductors elements. At high frequencies or packages with high inductance, the package can influence the ESD event waveform and the circuit response.

3.8 ESD Time Constants

3.8.1 ESD time constants

To understand physical phenomena, and particularly ESD phenomenon, it is necessary to quantify the scale in both space and time. ESD phenomena involves microscopic to macroscopic scales. ESD phenomena involves electrical and thermal transport on the scale of nanometers, circuits and electronics on the scale of micrometers, semiconductor chip designs on the scale of millimeters, and systems on the scale of meters. The time scales of interest range from picoseconds (ps) to microseconds (ms). Electrical currents of interest range from milliamps (mA) to tens of amperes (A). The voltage range of interest varies from volts (V) to kilovolts (kV). Temperatures vary from room temperature to melting temperatures of thousands of degrees Kelvin. It is the vast ranges of time, space, currents, voltages, and temperature as well as its transition from the microscopic to the macroscopic which makes ESD phenomenon difficult to model, simulate, and quantify.

To comprehend ESD phenomenon and establish validity of analytical developments, it is important to be able to understand what phenomenon is important. By analyzing the physical equations from a time constant approach, equations and understanding can be made both rigorous as well as improve logical clarity.

3.8.2 ESD events

To understand the role of ESD events and the physical environments, it is important to quantify the characteristic times of an ESD event. ESD events are represented as circuit equivalent models. FIG. 3 contains the ESD time constant hierarchy.

3.8.3 Human body model characteristic time

A fundamental model used in the ESD industry is known as the HBM pulse. The model was intended to represent the interaction of the electrical discharge from a human being, who is charged, with a component or object. The model assumes that the human being is the initial condition. The charged source then touches a component or object using a finger. The physical contact between the charged human being and the component or object allows for current transfer between the human being and the object. A characteristic time of the HBM is associated with the electrical components used to emulate the human being. In the HBM standard, the circuit component to simulate the charged human being is a 100 pF capacitor in series with a 1500 ohm resistor. This network has a characteristic rise time and decay time. The characteristic decay time is associated with the time of the network

_HBM = RHBMCHBM

where RHBM is the series resistor and CHBM is the charged capacitor. This is a characteristic time of the charged source. A more accurate understanding of the waveform and time constant is needed to evaluate the circuit response. The RC time constant only addresses the decay time of the waveform, and does not quantify the rise time. A more accurate representation of the HBM event addresses the series inductance. Roozendaal treated the HBM waveform as a lumped RLC network consisting of the source capacitor, a series inductor, and series resistor. The current as a function of time from the HBM event can be expressed as a double exponential waveform

The addition of the inductor introduces an L/R time constant into the HBM waveform expression. This can also be expressed in as a hyperbolic form as the solution of the RLC network

FIG. 3 Electrostatic discharge (ESD) time constant hierarchy

...where the resonant frequency is …

For the HBM pulse waveform, the R/2L time constant is greater than the LC resonant time constant. The rise time is dominated by this time constant, where…

The inductance in the HBM simulators are in the range of 5-10 mH, leading to rise times of the order of 17-22 ns.

3.8.4 Machine model characteristic time

Another fundamental model used in the ESD industry is known as the machine model (MM) pulse. The model was intended to represent the interaction of the electrical discharge from a conductive source, which is charged, with a component or object. The model assumes that the ''machine'' is charged as the initial condition. The charged source then touches a component or object. In this model, an arc discharge is assumed to occur between the source and the component or object allowing for current transfer between the charged object and the component or object. A characteristic time of the machine model is associated with the electrical components used to emulate the discharge process. In the MM standard, the circuit component is a 200 pF capacitor with no resistive component. An arc discharge fundamentally has a resistance on the order of 10-25 ohm. The characteristic decay time is associated with the time of the network

…where R is the arc discharge resistor and C is the charged capacitor. This is a characteristic time of the charged source.

The simplified expression does not address the waveform observed from test simulators.

The MM waveform contains both oscillation and an exponential decay. The current waveform as a function of time for the simulated MM pulse is ...

In this form, it is apparent that the waveform peak is a function of the initial voltage on the source capacitor. The oscillatory nature of the MM waveform is a function of the LC time constant. The damping factor is a function of the R/L time constant; as the R/L time constant increases, the current waveform decays at a faster rate.

3.8.5 Charged device model characteristic time

The CDM represents an ESD interaction between a chip and a discharging means where the chip is pre-charged. The charging process can be initiated by direct charging or field-induced charging. The discharge process is initiated as contact is initiated between the charged device and the discharging means.

3.8.6 Charged cable model characteristic time

Another fundamental model used in the ESD industry is known as the charged cable model or cable model pulse. The model was intended to represent the interaction, the electrical discharge of a charged cable, discharging to a chip, card or system. To initiate the charging process, a transmission line or cable is dragged on a floor leading to tribo-electric charging.

The model assumes that the cable is charged as the initial condition. The charged cable source then touches a component or object. A characteristic time of the cable model is associated with the electrical components used to emulate the discharge process. In the charged cable model, the cable acts as a capacitor element. The characteristic decay time is associated with the time of the network

...where R is the discharge resistor and C is the charged cable. The capacitance used for this model is 1000 pF. In early development times, this model was treated as an RC response model, where a very large capacitor represented the cable.

3.8.7 Cable discharge event (CDE) model

In recent years, this model has evolved into the cable discharge event (CDE) model.

In early development, this was a concern for large system cables. System level engineers are required to improve system-level performance while maintaining the quality and reliability.

ESD and electromagnetic emissions (EMI) are a concern in systems. System level standards and system engineers have long known that charged cables can also introduce system-level concerns. Charge accumulation on unterminated twisted pair (UTP+ cables occur through both tribo-electric charging and induction charging. In the case of tribo-electrification, in a UTP cable can be dragged along a floor. A positive charge is established on the outside surface of the insulating film. The positive charge on the outside of the cable attracts negative charge in the twisted pair leads across the dielectric region. When the negative charge is induced near the outside positive charge, positive charge is induced in the electrical conductor at the ends of the cable. As the cable is plugged into a connector, electrical arcing will occur leading to a charging of the unterminated twisted pair (note: the twisted pair was neutral to this point). If a cable is introduced into a strong electric field, induction charging will occur. When the electric field is removed the cable remains charged until a discharge event from grounding occurs. With the integration of wide area networks (WAN), and local area network (LAN), the Ethernet is playing a larger role. When a charged twisted pair cable connects to an Ethernet port with a lower electrical potential, cable discharge events can occur in LAN systems. In the past, standards (e.g., IEEE 802.3 Section 14.7.2) have noted the potential for CDE processes in LAN cables. Additionally, the introduction of Category 5 and Category 6 cables have significantly low leakage across the dielectric. As a result, when a tribo-electric charge is established, the conductance of the insulator is so low that the induced charge can maintain for long time scales (e.g., 24-h period). The CDE produces a rectangular pulse whose pulse width is a function of the length of the cable, L.

The pulse width can be expressed as follows:

3.8.8 Charged cassette model characteristic time

The charged cassette model (CCM) is a recent model associated with consumer electronics.

In consumer electronics there are many applications where a human plugs a small cartridge or cassette into a electronic socket. These are evident in popular electronic games. In today's electronic world, there are many palm-size electronic components which must be inserted into a system for non-wireless applications. To verify the electronic safety of such equipment, the cassette itself is assumed as a charged source. The ''cassette model'' assumes a small capacitance and negligible resistance. This model is equivalent to a machine model type current source with a much lower capacitor component. The model assumes the resistance of an arc discharge and a capacitance of 10 pF.

3.8.9 Transmission line pulse (TLP) model characteristic time

Transmission line pulse (TLP) testing has seen considerable growth in the ESD discipline. In this form of ESD testing, a transmission line cable is charged using a voltage source. The TLP system discharges the pulse into the device under test (DUT). The characteristic time of the pulse is associated with the length of the cable.

The pulse width of a TLP is a function of the length of the transmission line and the propagation velocity of the transmission line. The propagation velocity is can be expressed relative to the speed of light, as a function of the effective permittivity and permeability of the transmission line source.

TLP systems are designed in different configurations. TLP system configurations include current source, time domain reflectometry (TDR), time domain transmission (TDT), and time domain reflectometry and transmission (TDRT). In all configurations, the source is a transmission line whose characteristic time constant is determined by the length of the transmission line cable. The various TLP configurations influence the system characteristic impedance, the location of the DUT, and the measurement of the transmitted or reflected signals.

For this method, the choice of pulse width is determined by the interest to use TLP testing as a equivalent or substitute method to the HBM methodology. The standard practice today, the TLP cable length is chosen as to provide a TLP pulse width of 100 ns with less than 10 ns rise time.

3.8.10 Very fast transmission line pulse (VF-TLP) model characteristic time

Very fast TLP (VF-TLP) test method is similar to the TLP methodology. The interest in VF-TLP testing is driven by the desire to have an understanding semiconductor devices in a time regime similar to the CDM time constant. The characteristic time of interest is again determined by the propagation characteristics of the transmission line cable source and the length of the transmission line cable.

F-TLP pulse width of interest is a pulse width of less than 5 ns and a sub-1 ns rise time. This time regime is well below the thermal diffusion time constant in semiconductor media. The method of the fast time constant limits the acceptable configurations of the VF-TLP system and suitable equipment for measurement.

4. CAPACITANCE, RESISTANCE, AND INDUCTANCE AND ESD

4.1 The Role of Capacitance

In the understanding of ESD events, it is important to understand the role of capacitance, resistance, and inductance and where it comes into play in the analysis. Capacitance has a role in the capacitive loading effects in networks, timing circuits, as well as charge storage, charge distribution, and displacement current in ESD events. In ESD design, capacitance has a role in the following environments:

_ Capacitance loading effects of ESD protection networks for signal pads.

_ RC-discriminator networks for frequency-dependent trigger networks for signal and power pads.

_ Current distribution within an ESD network at high speed and radio frequency (RF) GHz applications.

_ Current distribution within a chip power rails and power grid.

_ Chip or system impedance (e.g., Z = 1=j w C).

_ LC transmission lines for RF applications.

Capacitance loading effects are a concern for receiver networks because it impacts circuit performance objectives. As the application frequency increases, circuit designs desire to lower the ESD input network capacitance loading. For example, in some applications it is desired to maintain a constant reactance, then as the functional frequency increases, the ESD loading capacitance decreases accordingly.

Capacitance also plays a role in trigger networks which tune the RC time constant so that the ESD network responds to the ESD pulse. Circuits are designed to respond to the ESD impulse but not to the power-up or functional frequencies, discriminating the response to ESD events instead of functional applications.

For RF applications, the role of the capacitance influences the frequency response of the ESD network as well as its location on a Smith Chart.

Capacitance also plays a role in the way in which current distributes through a semiconductor chip power grid. The capacitance per unit distance of the power bus plays a role in how the current distributes within a semiconductor chip.

Capacitance plays a role in the impedance (or effective impedance) of the whole chip.

The chip or system impedance (e.g., Z = 1=j w C) plays a key role in the ability to displace current across the chip (note: I = C dV=dt). In RF applications, capacitance plays a role in the LC transmission line elements used in RF applications.

Hence, the understanding of lumped and distributed capacitance is fundamental in ESD events. Capacitance is key from the local ESD element, circuits as well as the global capacitance components of a semiconductor chip. It can be observed locally within a semiconductor device, a circuit or globally on a chip level.

4.2 The Role of Resistance

Resistance is one of the most important parameter in ESD events. The role of resistance is critical in the voltage and current distribution within a semiconductor device, circuit, or network. The understanding of resistance and the resistance distribution plays a more significant role compared to inductance and capacitance issues. Typically, inductance plays an important role in the effect of lead frames and packages on the ESD response, but play a minor role in the understanding of ESD devices and circuit response in semiconductor chip environments. Capacitance also plays a key role when the RC time of the wiring is of the order of the characteristic time of the event. Hence, the understanding of lumped and distributed resistance systems is fundamental in ESD events. Resistance plays a key role from the local current distribution within a diode structure, a MOSFET structure, off-chip driver circuits, to global current distribution in the metal busses, and the chip substrate.

In ESD design, resistance has a role in the following environments:

_ Voltage distribution and on-resistance within an ESD protection structure.

_ Voltage distribution and on-resistance within the protected circuit.

_ Voltage and current distribution through the power grid.

_ Voltage and on-resistance of the ESD power clamps.

_ RC-discriminator networks for frequency-dependent trigger networks for signal and power pads.

_ Current distribution within an ESD network at high speed and radio frequency (RF) GHz applications.

Resistance plays a fundamental role in the operation of an ESD protection circuit. Voltage distribution and on-resistance within an ESD protection structure is critical in order to provide an effective ESD structure. Additionally, the resistance also plays a role in the Joule heating within the ESD structure.

The voltage distribution and on-resistance within the protected circuit is also critical in the understanding of the failure of an ESD network. The voltage and current distribution

through the power grid is critical in that it influences the peak voltage and current in the system. Resistance also plays a role in the way in which current distributes through a semiconductor chip power grid. The resistance of the power grid also decreases the voltage margin between the ESD current path and the voltage at the protected circuit of interest.

These factors can drive the effectiveness of the ESD strategy, and can determine power clamp circuit placement.

In the ESD power clamps, the net resistance also plays a role in the ESD event. The resistance of the power grid also decreases the voltage margin between the ESD current path and the voltage at the protected circuit of interest.

Hence, the understanding of lumped and distributed resistance is fundamental in ESD events. Resistance is key from the local ESD element, circuits as well as the global capacitance components of a semiconductor chip. It can be observed locally within a semiconductor device, a circuit, or globally on a chip level.

4.3 The Role of Inductance

In the understanding of ESD events, it is important to understand the role of inductance and where it comes into play in the analysis. Inductance has a lesser role compared to resistance and capacitance effects. Inductance primary role occurs in package lead frames, wire bonds, package pins, and the package itself. In analog and mixed signal (A&MS), RF CMOS, and RF BiCMOS applications, inductors are used in circuits for dc-biasing and blocking, LC transmission lines, LC tank circuits, and other RF circuit applications. In ESD design, inductance has a role in the following environments:

_ Packaging lead frames.

_ Package wire bonds.

_ Package pins.

_ RF circuit elements-LC transmission lines.

_ RF circuits with dc-biasing.

_ RF ESD circuits.

Package lead frames and wire bonds can influence the inductive coupling between power rails and influence circuit response. To reduce the on-chip noise, power rails are reconnected at the package lead frame, or pads, or at the package. In this fashion, the package inductance plays a role in the response of peripheral circuits which have disconnected power and ground rails on the chip.

Inductance is also playing a more critical role with the introduction of inductors and transmission lines as design elements. Inductors are used in dc-biasing networks, LC tank circuits and are being introduced into ESD networks. Inductors are being introduced to provide distributed networks isolated for lowering the effective loading of ESD elements. As a result, the understanding of lumped and distributed LC transmission lines in key to understanding the effect of inductance on ESD events. Hence, the understanding of lumped and distributed inductance is fundamental to ESD understanding in packaging and RF applications.

5. RULES OF THUMB AND ESD

5.1 ESD Design an ''ESD Ohm's Law'': A Simple ESD Rule-of-Thumb Design Approach

In the semiconductor industry, the ability to understand the influence of ESD on semi conductor chips is difficult for those who are not semiconductor device engineers or circuit designers. An ''ESD Ohm's Law'' is needed to provide a simplistic but adequate ESD design practice. A simple rule-of-thumb for analysis was needed for design sizing and estimation.

The following ESD Ohm's law rule-of-thumb approach is recommended:

_ Determine the voltage of the dielectric breakdown or MOSFET snapback of the circuit that requires protection.

_ Find all the turn-on voltages and effective resistances through the chip from the input pad to the chip ground plane substrate and estimate the resistances to the nearest ohm in the ''ESD current loop.''

1. ESD element.

2. Wire bussing between the signal pad and the nearest ESD power clamp.

3. ESD power clamp.

_ In the case of a chip without an ESD power clamp, assume a frequency of the ESD pulse, and a total chip capacitance to evaluate the net impedance (e.g., Z = 1=j w C where w is the ESD pulse of interest). Assume a frequency associated with 100 ns for HBM, 10 ns for MM, and 1 ns for CDM events.

_ Assume a 1 A direct current (dc) flowing through the ESD current loop circuit and evaluate the sum of the voltage drops in the ''ESD current''

__ where VT is the total voltage drop, and within the summation, VT is the turn-on voltage and R is the resistance of the elements in the ESD current loop path. The summation is the sum of all elements in the ESD current loop path (FIG. 4).

FIG. 4 ESD current path

_ Evaluate the voltage margin between VT and the failure voltage of the protected circuit, Vf. This determines the voltage margin to failure.

_ If the voltage margin is positive, there is margin prior to circuit failure. If the voltage margin is negative, the protected network will fail prior to distributing 1 A of current.

This simple development is useful as a rule-of-thumb analysis without semiconductor device design tools and circuit simulation. This method will allow a quick understanding of the resistances and turn-on voltages in order to design an effective strategy. From this method, one can have a sense of the size of the ESD element, the bus widths, and the size of the ESD power clamp. Additionally, in many large chips, knowing the chip impedance, one can determine if an ESD power clamp is necessary.

6. LUMPED VERSUS DISTRIBUTED ANALYSIS AND ESD

6.1 Current and Voltage Distributions

To provide an effective ESD design strategy, the ESD design practices must focus on the local and global distribution of electrical and thermal phenomena in devices, circuits, and systems. In order to shunt the ESD current efficiently and effectively, the distribution of the current is critical in ESD design. As the current distributes, the effectiveness of the device improving the utilization of the total area of the ESD network or circuit element. On a circuit and system level, the distribution of the ESD current within the network or system lowers the effective impedance and the voltage condition within the ESD current loop. A key design practice and focus in ESD development is the distribution effects. The ESD events are transient events; the physical time constants of the devices, circuits, and systems are critical in the understanding, modeling, and simulation of the effectiveness of the elements in the system. A key design practice of ESD devices and circuits is the desire to distribute the current to provide improved design utilization to achieve higher ESD robustness.

6.2 Lumped versus Distributed Systems

In the analysis of ESD events, the understanding of the current and voltage distribution within a semiconductor device, a circuit, or a chip is important for modeling, evaluating the efficiency, as well as quantifying the area of the network which is involved in space and in time.

In devices, circuits, interconnects, ESD circuits, and even test equipment, the distribution of voltage and current is key to understanding as well as analysis. In ESD phenomenon, voltage drops occur in the metal wiring pattern of single- and multi-finger elements such as diodes and MOSFETs form distributed current distribution. Off-chip driver (OCD) networks are also sensitive to the current and voltage distribution at these high-current levels. The metal bus of the power rail and the ground rail also has a role in the ESD analysis. The semiconductor substrate also serves as a lossy distributed region where current is flowing.

Additionally, even the test equipment utilize transmission line cables for forming the ESD test in TLP testing and very fast-transmission line pulse (VF-TLP) systems.

In the case of modeling ESD events in devices, circuits, or chips, the question arises of whether the element or network should be treated as a single lumped element, or a distributed element. The decision of treating an element as a lumped element, or a distributed set of elements (e.g., a ladder network or a transmission line) can be quantified as a competition between the rise time of an ESD event and the time of flight through the network.

Let us define the time of flight as …where l is the length of the structure, and v is the propagation velocity.

When some integer number of the time of flight is larger than the ESD event rise time, then the network should be modeled as a ladder network or distributed network. When some integer number of the time of flight is less than the rise time, the network can be treated as a lumped element.

In transmission line theory, a rule-of-thumb used is if the rise time is equal to tr < 2:5_ then the structure should be modeled as a ladder network or transmission line.

When the ESD event rise time is significantly slower than the time of flight, the voltage is not uniform. Hence in cases of HBM pulses, whose rise time is 17-22 ns, if the structure is such that the time of flight is approximately 10 ns, the structure should be modeled as a transmission line. In the transmission line theory, the structure can be modeled as a lumped capacitor element if tr > 5 tau. Hence, when the rise time is greater than five ''bounce'' times, the system can be treated as a single component element. This analysis is valid for understanding of the voltage distribution in packaging, power grids, and substrates where there is a low-loss component.

In the case of lossy systems, where resistance has a dominant role, the voltage drops in the system also play a significant role in the modeling as a lumped or distributed system.

During ESD events, the resistance plays an important role in the power bus, the ESD element, and ESD power clamps.

A good rule-of-thumb for ESD events in the decision of whether the device, circuit, or power grid should be treated as a lumped or distributed system should be as follows:

_ When the ESD current through the system introduces voltage drops greater than 0.25 V, the element should be separated into a distributed network.

One reason for this rule-of-thumb is that ESD structures incorporate forward-bias diode elements on the order of 0.7 V. When the voltage drop across the device is greater than 0.25, some sections of the device are forward active, and some are not. In this case, the element should be separated into a resistance-diode ladder network.

A second reason for this rule-of-thumb is the resistance in the power bus are of 0.25-5 ohm.

When 1 A of current is forced through the power bus, the voltage drops will be of the order of 0.25-5 V; for the case of 3 A, the results are greater than 1 V drop. At these levels, the input circuit will see a higher voltage on the input node of this magnitude. Hence, the power rail should be segmented into a resistance-conductance (RG) ladder network, or a resistance-capacitance (RC) ladder network.

6.3 Distributed Systems: Ladder Network Analysis

In the understanding of distributed networks and ESD protection evaluation, it is important to obtain how the ESD current distributes along a structure. Treating the ESD element as a distributed two-port network, we can treat the input side as the port (1) and the output side as port (2). In the two-port network, we can quantify the impedance distribution between the input port and the output port by treating the network as a ''ladder network'' consisting of impedances along the top of the network (numbered in an odd succession), and as admittances between the top and bottom (numbered in an even succession). FIG. 5 shows a ladder network. The ladder network is used in the treatment of analysis for ESD design in MOSFETs. The voltage and current can be expressed as

By applying conditions to the current and voltages at the input and output port, the z-parameters can be solved for. To solve for the impedance term z11 of the matrix, we can let the output current to be equal to zero

The impedance can be expressed as the sum of first impedance element and the impedance looking into the network (which we will designate alphabetically)with the corresponding admittance

FIG. 5 Two-port ladder network

The admittance term can be expressed as the sum of the first admittance term and the inverse of the impedance looking in

Substituting this into the impedance term, we can express this as ...

This step can be repeated continuously down the rungs of the ladder network as...and...and repeated to the last admittance element.

In this form, the impedance term is expressed as the Stieljes continued fraction. The solution for the output impedance term z22 (s) can be solved in the same manner, but reversing the process.

For ESD analysis of the dc or ac frequency response, the ability to quantify a resistor, a diode, or a MOSFET as a distributed system allows to quantify the ESD efficiency at which an ESD structure or I/O network distributes the ESD current. All the distributed models discussed in ESD analysis are forms of the ladder network but using either different mathematic techniques or boundary assumptions. One of the distinctions is that when the ladder network is traversed, there are voltage drops or ''on state'' assumptions to connect the two electrodes.

6.4 Resistor-Inductor-Capacitor (RLC) Distributed Systems

Resistance, inductance, and capacitance play a role in the voltage and current distribution during ESD events which address inductive components, lossy transmission lines, lead frames, and packaging effects.

On a semiconductor device level, typically inductive effects are not an issue unless inductor components are added to the network. In RF CMOS and RF BiCMOS networks, inductors are present as lumped elements. In some ESD networks, the lumped components are used as a plurality of elements to form a multiple lumped-element distributed network.

The multiple lumped-element networks take advantage of the transmission line nature of a distributed system. Hence, although they are lumped components, the complete ESD network behaves as a distributed network.

Transmission lines (T-lines) are also formed in RF components as components between the pads and receiver networks. Typically, these are low-resistance components formed using metal films.

Transmission lines are also present in the ESD test systems themselves. TLP systems incorporate transmission lines in the network to initiate and shape the pulse to simulate ESD events.

On a global chip level, inductance plays a role in the power bus, ground bus, wire bonds, package lead frames, and pins. In the analysis of the current distribution during an ESD event, inductive effects can play a role.

The incremental variation also plays a role in the voltage and current response during high-current ESD operation. To analyze the incremental variation from point z to a second point (z ) dz), assume a resistance term R(z)dz where R(z) is the resistance per unit length over increment dz.

In series with the resistance element, an inductor is added of the form L(z) dz where L(z) is the inductance per unit length over increment dz. Between the top surface and bottom surface of the transmission line, there is a capacitor per unit distance C(z) dz. In parallel with the capacitance, a conductance term, G(z) dz is added where G(z) is the conductance per unit length over increment dz.

Forming a two-port network where the input current is I(z; t), and input voltage V(z; t) at input port z, and the output current I(z ) dz; t) and output voltage V(z ) dz; t), a coupled set of equation can be formed with differential voltage can be represented as the voltage potential difference across resistance R(z) dz as well as the voltage drop across the incremental inductor L(z)dz ...

...and the differential current can be represented as the charge across the capacitor C(z) during increment of time dt, and current through the conductance term ...

This can be expressed as a set of coupled differential equations as …

The above coupled equations are the transmission line equations for an RLC-transmission line. FIG. 6 shows the RLC incremental model. Taking the partial derivative of the voltage distribution equation with respect to space

FIG. 6 Incremental model of RLC distributed system

From the coupled equations, we can solve for second term by taking the partial derivative of current with respect to time,

The above equation is the general expression for an increment where resistance, conductance, capacitance, and inductance are incorporated.

In this case the conductance is much small, and the RC product is much larger than LG, the special case reduces to…

In this case the conductance is small, but the RC product is much smaller than the LG product FIG. 7 Incremental model of inductor-capacitor (LC) distributed system...

In the case that the conductance and the resistance are small compared to the inductance and capacitance, this reduces to the elliptical equation, also known as the wave equation ...

Hence, when the resistive and conductance terms tend to zero, the voltage and current distribution follows the form of the wave equation. FIG. 7 shows the incremental model for the LC network. The wave equation can be put in the form of a velocity times the time expressed as ...

...where phase velocity is defined as ...

The characteristic impedance of a lossless transmission line is also related to the ratio of the inductance to the capacitance, expressed as

From this analysis, the nature of the voltage and current distribution is a function of the assumptions of the inductance, capacitance, resistance, and conductance terms. From the two limiting cases, of small resistance and conductance terms, the equations will have the form of a lossy transmission lines. Placing the last term on the RHS

This form is known as the damped wave equation.

Note when the term on the RHS is weak, the nature of the system still behaves as a transmission line with loss associated with the resistance and conductance. But when the LC time is small, the system reduces to the equation, which is dispersive in nature. From an ESD perspective, the RC distributed system, and RG distributed system limits are prevalent in both device and chip level response in most cases.

Substitution of the second coupled equation

Assuming a constant coefficient for the resistance and capacitance, the voltage equation is reduced to a second order partial differential equation in space and time

The second order partial differential equation is the parabolic (or diffusion) equation. The parabolic equation is first order in time and second order in space. This is referred to as the voltage diffusion equation. Hence, the characteristic time constant of the system is related to the local RC time of the increment. Assuming a step impulse from an ESD event, one can solve for the solution using a Laplace transformation operator L ...

Substituting in the Laplace transformed terms into the voltage diffusion equation, the second-order partial differential equation in space and time is reduced to a second-order O[2] differential equation in the variable z,

For a second order ordinary differential equation, there are two solutions which can be expressed as a function of voltage coefficients .....

In this analysis, one of the solutions will increase to infinity. As a result, we can assume that one of the two solutions is not physical. The solution that decays with distance is the physical solution. Assuming a step input voltage at the V(z = 0; t) equal to an initial voltage step V0 u(t), and from the Laplace transform of a step function (e.g., 1/s) the solution by inspection can be determined to be ......

Using the inverse Laplace transformation, the solution can be expressed as the complimentary error function

From the current-voltage relationships, solving for the current and taking the partial derivative with respect to position........

Taking the derivative....

An analogy can be established to semiconductor carrier diffusion or heat diffusion, where there exists a characteristic diffusion length, and diffusivity coefficient for the RC network.

This is related to the argument within the error function (and the exponential term). From the above solution, the current decreases according to the product of the inverse of time and an exponential function related to the square of the distance. The magnitude of the exponential term is a function of the ratio of the characteristic time relative to the RC time of the network.

In the distributed RC network, the voltage and current distribution is a function of the time, position, and the characteristic resistance and capacitance of the network. Hence, the spatial and temporal distribution of the voltage and current is a function of the characteristic time constant, RC, and the time scale, t. In the understanding of current and voltage distribution within an ESD device, or the distribution within a chip, the ratio of the characteristic time to the product of the resistance and capacitance (e.g., RC time constant) is a key ESD design criteria.

6.5 Resistor-Capacitor (RC) Distributed Systems

Resistance and capacitance play a fundamental effect on the voltage and current distribution during ESD events. Typically, inductive effects can be ignored when evaluating the voltage and current distribution on a semiconductor chip. Hence, the understanding of lumped and distributed resistance-capacitor systems is fundamental in ESD events. The resistance and capacitance can be observed locally within a semiconductor device, a circuit or globally on a chip level. Even in small devices, metal bussing plays a role in the resistance within the device where metal line widths are small. For example, an ESD diode element can be represented as a anode metal bus with a given resistance per unit micron. Additionally, the diode element can be represented as a capacitor element.

On a semiconductor chip level, although the metal bus widths are large, the distances of interest are on the scale of the semiconductor chip, or distance between input nodes, and power pads. In this case, the wide bus resistance per unit length and the capacitance form a resistance- capacitor (RC) transmission line which can influence the voltage and current distribution during ESD events. As a result, the resistance and the capacitance play a key role from the local response of a single device, to the global response of chip architecture during an ESD event.

The incremental variation plays a role in the voltage and current response during high current ESD operation. To analyze the incremental variation from point z to a second point (z ) dz), assume a resistance term R(z) dz where R(z) is the resistance per unit length over increment dz. Between the top surface and bottom surface of the transmission line, a capacitor per unit distance C(z) dz. Forming a two-port network where the input current is I(z; t), and input voltage V(z; t) at input port z, and the output current I(z ) dz; t) and output voltage V(z ) dz; t) a coupled set of equation can be formed with differential voltage can be represented as the voltage potential difference across resistance R(z) dz ...

... and the differential current can be represented as the charge across the capacitor C(z) during increment of time dt .......

The above coupled equations are the transmission line equations for an RC-transmission line.

Taking the partial derivative of the voltage distribution equation with respect to space, ...

The second order partial differential equation is the parabolic (or diffusion) equation. The parabolic equation is first order in time and second order in space. This is referred to as the voltage diffusion equation. Hence, the characteristic time constant of the system is related to the local RC time of the increment.

Assuming a step impulse from an ESD event, one can solve for the solution using a Laplace transformation operator L ...

Substituting in the Laplace transformed terms into the voltage diffusion equation, the second-order partial differential equation in space and time is reduced to a second-order differential equation in the variable z

For a second-order ordinary differential equation, there are two solutions which can be expressed as a function of a voltage coefficients ....

In this analysis, one of the solutions will increase to infinity. As a result, we can assume one of the two solutions is not physical. The solution that decays with distance is the physical solution. Assuming a step input voltage at the V(z = 0; t) equal to an initial voltage step V0 u(t), and from the Laplace transform of a step function (e.g., 1/s) the solution by inspection can be determined to be…

Using the inverse Laplace transformation, the solution can be expressed as the complementary error function ...

From the current-voltage relationships, we can also solve for the current and taking the partial derivative with respect to position.....

Taking the derivative, we have....

An analogy can be established to semiconductor carrier diffusion or heat diffusion, where there exists a characteristic diffusion length and diffusivity coefficient for the RC network.

This is related to the argument within the error function (and the exponential term). From the above solution, the current decreases according to the product of the inverse of time and an exponential function related to the square of the distance. The magnitude of the exponential term is a function of the ratio of the characteristic time relative to the RC time of the network.

In the distributed RC network, the voltage and current distribution is a function of the time, position, and the characteristic resistance and capacitance of the network (FIG. 8).

Hence, the spatial and temporal distribution of the voltage and current is a function of the characteristic time constant, RC, and the time scale, t. In the understanding of current and voltage distribution within an ESD device, or the distribution within a chip, the ratio of the characteristic time to the product of the resistance and capacitance (e.g., RC time constant) is a key ESD design criteria.........

FIG. 8 Incremental model for resistor-capacitor (RC) distributed system

6.6 Resistor-Conductance (RG) Distributed Systems

Resistance is the most important parameter in ESD events. The role of resistance is critical in the voltage and current distribution within a semiconductor device, circuit, or network. The understanding of resistance and resistance distribution plays a more significant role compared to inductance and capacitance issues. Typically, inductance plays an important role in the effect of lead frames and packages on the ESD response, but play a minor role in the understanding of ESD devices and circuit response. Capacitance plays a role when the RC time of the wiring is of the order of the characteristic time of the event. Hence, the understanding of lumped and distributed resistance systems is fundamental in ESD events.

Resistance plays a key role from the local current distribution within a diode structure, a MOSFET structure, off-chip driver circuits, to global current distribution in the metal busses, and the chip substrate.

The incremental variation plays a role in the voltage and current response during high current ESD operation in the resistive network. To analyze the incremental variation from point z to a second point (z ) dz), assume a resistance term R(z) dz where R(z) is the resistance per unit length over increment dz (FIG. 9). Between the top and bottom surface of the transmission line, a conductance per unit distance G(z) dz. Forming a two-port network where the input current is I(z; t) and input voltage V(z; t) at input port z, and the output current I(z ) dz; t) and output voltage V(z ) dz; t), a coupled set of equation can be formed with differential voltage represented as the voltage potential difference across resistance R(z) dz

…and the differential current loss can be represented as the differential current through a conductance term G(z)

This can be expressed as a set of coupled differential equations as

[...]

FIG. 9 Incremental model for the resistor-conductance (RG) distributed model

In the analysis of the RG ladder network, as the current and voltage extends down the network, the voltage decreases in an exponential fashion according to the spatial parameter of the arithmetic mean of the incremental resistance and the incremental conductance. As the resistance or the conductance increases, the voltage decay along the transmission line increases. Also note that as the resistance and conductance tend to zero, the voltage approaches a constant value and the current tends to zero.

7. ESD METRICS AND FIGURES OF MERIT

ESD metrics and ESD figures of merit (FOM) can be established to provide a means of quantifying and benchmark, the value of the ESD protection strategy. ESD metrics and FOM can be established on a system, chip, circuit, and device level to address the macro-level and micro-level effectiveness of the ESD protection methodology and strategy.

On a chip level, there are measures that provide value add meaning in the quantification of the ESD chip strategy for the given chip design in the semiconductor process. Useful chip level ESD metrics include the following:

_ Chip mean pin power-to-failure.

_ Chip pin standard deviation power-to-failure.

_ Chip mean pin power-to-failure to ESD specification margin.

_ Worst case pin to specification ESD margin.

_ Total ESD area to total chip area ratio.

7.1 Chip Level ESD Metrics

7.1.1 Chip mean pin power-to-failure

Chip mean pin power-to-failure is the mean of the pin power-to-failure distribution within a semiconductor chip. Within a semiconductor chip, the power-to-failure is a function of the semiconductor process, the peripheral circuit library, the ESD input protection networks, and the power grids. The variation within a semiconductor chip is a function of the types of circuits, and types of ESD elements used. The pin-to-pin variation of an identical pin can be associated with semiconductor process variations within a given chip (e.g., photolithography, etch, and film thickness variations), the power bussing, the ESD power clamp placement, and other design-related features.

The chip mean power-to-failure is the average peak value where the distribution is centered.

7.1.2 Chip pin standard deviation power-to-Failure

The chip pin standard deviation power-to-failure is the standard deviation associated with the pin power-to-failure distribution across a given chip. As stated above, the variation within a semiconductor chip is a function of the types of circuits and types of ESD elements used. The pin-to-pin variation of an identical pin can be associated with semiconductor process variations within a given chip (e.g., photolithography, etch, and film thickness variations), the power bussing, the ESD power clamp placement, and other design-related features. The standard deviation is also influenced in the variety of different size I/O networks that are contained within the chip. The ESD metric can be referenced as the power to-failure or the variation in the ESD robustness for a given device model (e.g., human body model, machine model).

7.1.3 Chip mean pin power-to-failure to ESD specification margin

Chip mean pin power-to-failure (ESD) to power-to-failure (ESD) specification margin is the margin between the actual mean of the power-to-failure pin distribution within a semi conductor chip and the product specification. The importance of this ESD metric is by evaluating the margin of the mean relative to the specification, an understanding of the effectiveness of the ESD design strategy as well as the robustness of the technology can be evaluated. As the ESD robustness of a process technology improves, the mean chip power to-failure distribution will increase (e.g., for a given fixed ESD design strategy). Addition ally, when a better ESD network is utilized, the ESD failure distribution will shift relative to the specification (e.g., for a given fixed semiconductor process technology). This ESD metric is important to evaluate the ESD robustness of a technology, and the effectiveness of the ESD network to protect the circuits within the technology.

7.1.4 Worst-case pin power-to-failure to specification ESD margin

The worst-case pin power-to-failure to specification ESD margin is a measure of the difference between the worst-case pin in the ESD pin distribution relative to the defined ESD specification. In the case of the worst-case pin, this may be a function of a given circuit, or can be associated with the standard deviation, and the mean chip power-to-failure. In the case that the difference between the mean chip power-to-failure and the power-to-failure specification level is small, and the pin power-to-failure standard deviation level is also wide, then the worst-case pin power-to-failure may be on the power-to-failure distribution ''tail.'' In this case, the ESD protection strategy or the semiconductor process must be altered to establish an increase in the margin between the worst-case pin and the ESD specification level.

In many cases, the worst-case pin failure may be associated with different peripheral circuits, and are not contained within the Gaussian or normal distribution of pin failures. For example, receiver networks may not be contained within the I/O OCD failure distribution, but may represent its own power-to-failure distribution (e.g., and may contain a different failure mechanism). In this case, it is not always clear that the changes in the semiconductor process will lead to shift in the margin between the ESD specification and the worst-case pin failure level. In the case that it will track with the semiconductor process or ESD network, improving the mean power-to-failure distribution will lead to an increase in the margin between the worst-case pin and the ESD specification.

7.1.5 Total ESD area to total chip area ratio

An ESD metric of interest is the ratio of the total area utilized for ESD networks to the total chip area. This is a valuable metric for floor planning a design where the area on the chips are budgeted according to different functional objectives. For example, the peripheral circuit budget may be driven by Rents' Rule which relates the number of I/O relative to the number of logic gates. The area of a given I/O cell may be budgeted based on the number of I/O, and the desired ratio of the core logic relative to the peripheral I/O budget. In this floor planning metric, the amount of area for ESD protection may be budgeted to avoid utilization of excess design space.

AESD ()T A Chip

7.1.6 ESD area to I/O area ratio

A common ESD metric used in semiconductor chip floor planning is on the acceptable level of area of an I/O book utilized for ESD protection.

AESD () AI=O

In the floor planning of a microprocessor, or an ASIC design, the area dedicated to I/O is planned to be a certain percent area. In ESD design practice, the percentage of the I/O guide dedicated to the ESD protection is budgeted according to the above metric. In the past, the acceptable ratio ranged from 0.2 to 0.3.

7.2 Circuit Level ESD Metrics

The metrics for a given circuit are focused on both the performance degradation imposed with the addition of the ESD structure as well as the area consumption. Additionally, for circuits, the relationship between the ESD robustness of the circuit and the capacitance loading ratio is also a crucial ESD metric or FOM. Hence circuit-level ESD metrics are as follows:

_ Circuit ESD protection level to ESD loading effect.

_ Circuit performance to ESD loading effect.

_ ESD area to total circuit area ratio.

_ Circuit ESD level to specification margin.

7.2.1 Circuit ESD protection level to ESD loading effect

To evaluate the ESD protection level to the loading effect, the protection level is compared to the loading effect penalty. For example, given the loading effect is capacitive in nature, a circuit level ESD FOM can be represented as ...

... where the circuit level FOM is the ratio of the ESD voltage of failure to the capacitance of the ESD network. For example, the ESD voltage can be the HBM failure voltage. This provides a measure of the protection value add for the amount of capacitance added to the circuit.

7.2.2 Circuit performance to ESD loading effect

An important metric from a circuit designer's perspective is the effect of the capacitance loading effect on the performance of a circuit. Hence, an ESD metric that quantifies the loading effect as a percent decrease in the performance is of value to quantify the ESD impact on the circuit performance. This is achievable by the ratio of the difference of the ''unloaded'' circuit performance minus the ''ESD loaded'' circuit performance in the numerator and the ''unloaded'' circuit performance in the denominator.

P(w= o ESD)_ P(with ESD) P(w= o ESD)

In the past, the ESD loading effect was a minimal effect on the circuit performance. With technology scaling, the implications of the ESD loading effect has become more significant.

7.2.3 ESD area to total circuit area ratio

As in the total chip case, the budgeting of the area to functional utilization relative to the ESD protection is important for the understanding of the difficulty to ESD protect a given network and will determine its capability as the circuit is scaled AESD ACkt For example, in microprocessors in a 0.5-mm technology generation, the area ratio should be below 0.05 (5% area) for the ESD protection network.

7.2.4 Circuit ESD level to specification margin

A valuable ESD metric is the ESD margin between the circuit failure level and the specification. This provides an understanding of the ESD benchmarking of the given circuit in the technology and for that given circuit generation. As the circuit is scaled, or the technology is scaled, the understanding of how the circuit performs relative to the specification is critical to evaluate its future performance.

7.3 Device ESD Metric

ESD metrics of ESD devices can provide an insight in the value add of a given protection network. ESD metrics and figures of merit determine how much of the capability an ESD network can provide for a given design or ESD circuit type. The following metrics are used to evaluate the ESD design effectiveness:

_ ESD area percentage utilization factor.

_ ESD robustness to ESD loading effect ratio.

_ Power-to-failure to maximum power condition.

7.3.1 ESD area percentage utilization factor

This metric is a measure of the area efficiency of an ESD element. For a given width, W, and length L, a maximum area to minimum area factor can be defined, where the numerator is a maximum function, and the denominator is a minimum function for a geometry factor of

Max W; L fg Min W; L fg

This FOM can be used to evaluate area utilization and the efficiency of the area utilization of ESD protection.

7.3.2 ESD robustness to ESD loading effect ratio

On the ESD device level, the FOM for the ability to achieve a high-ESD robustness of a device of a given width and length, compared to the loading effect, is important for evaluation of the ESD device efficiency for achieving certain ESD levels for a given loading capacitance (e.g., impedance). This can be expressed as

FOM ()ESD= VESD W; L fg CESD W; L fg

7.3.3 Power-to-failure to maximum power condition

An ESD FOM is the maximum power-to-failure compared to the maximum functional power that a structure can maintain. For a given semiconductor device, the power-to-failure can be determined from the Wunsch-Bell model. The maximum power of a semiconductor device, such as a bipolar transistor, can be obtained from the Johnson Limit relationship. Hence, the ratio of the power-to-failure to the maximum power can be compared. This ratio forms a dimensional group relating the power-to-failure to the maximum functional power:

Pf PMax

7.4 ESD Quality and Reliability Business Metrics

In establishing an ESD strategy, quality, and reliability, ESD metrics can be established for measuring the success of the ESD implementation and strategy. Different corporations will have individual needs whose ESD metrics may differ according to the business quality model, business reliability objectives, or the state of the ESD strategy at a given time in the business strategy. The following are a few ESD business metrics utilized to measure the success of a corporate strategy:

_ Percentage of products above an ESD specification level (e.g., HBM specification of 2 or 4 kV).

_ Percentage of products above a given ESD specification on first design pass.

_ ESD plateau level (e.g., ESD protection mean level for all products vs. time).

_ ESD product learning rate (e.g., for HBM specification, kV/year).

_ Dollars Lost versus ESD protection level.

_ Yield loss versus ESD protection level.

The first ESD metric measures the ability to maintain a technology or number of technologies above a given ESD specification level. This is a measure of success at some point in the design release process.

The second ESD metric is a measure of the ability of ESD design success on first design pass. This ESD metric may be a measure of good ESD protection devices, good ESD design manuals, good ESD checking and verification, and robust circuits. This may be a demonstration of circuit designer training in ESD work and ESD design discipline.

The ESD protection plateau level is an ESD metric which may be a measure of the baseline of success of the ESD designs, technology robustness, and the ESD designer. The stability to a given ESD baseline may be a measure of the manufacturing control and ESD design discipline. The level of the ESD protection plateau may also be a measure that no ESD learning is in process and ESD design conservatism.

The ESD product learning rate can be a powerful metric in understanding the success of ESD semiconductor technology transitions, semiconductor scaling trends and a measure of success of new ESD implementations. In practice, over a number of years, the ESD trend can be evaluated to project either MOSFET scaling trends or implementation success. For example, a learning rate of 2 kV/year (HBM) from a 2 kV HBM ESD baseline by introducing semiconductor process changes, followed by ESD design layout improvements, followed again by OCD resistor ballasting, and finally adding RC-triggered ESD power clamps.

Another form of ESD metrics can be evaluated based on semiconductor manufacturing product losses, and losses as a function of ESD protection levels. For example, this can be measured as a function of dollar or yield loss in time or plotted as a function of the ESD protection level. These are a measure of the ESD control program, handling procedures, and the margin between the ESD sensitivity of the tooling and handling relative to the ESD product sensitivity.

8. TWELVE STEPS TO BUILDING AN ESD STRATEGY

In the practical implementation of an ESD program, there are a number of steps to be taken in delivering ESD sensitive parts successfully. In ESD program management, T. Dangel meyer noted twelve ''critical factors'' for building an ESD strategy from the product to the customer [100]. These are as follows:

_ Effective implementation plan.

_ Management commitment.

_ A full-time coordinator.

_ An active ESD committee.

_ Realistic requirements.

_ ESD training for measureable goals.

_ Auditing using scientific measures.

_ ESD test facilities.

_ A communication program.

_ Systematic planning.

_ Human factor engineering.

_ Continuous improvement.

The focus of this program is the management of a facility and corporation in managing its staff, tooling, and establishing corporate objectives.

To address the ESD design phase alone, there are also a number of critical steps that need to be taken. In order to achieve a good ESD design and release strategy, these 12 steps must be taken in order to insure consistent and acceptable ESD protection levels in a business that releases components which are sensitive to ESD. The following are 12 steps needed to insure an establishment of an ESD strategy:

1. ESD device and circuits strategy.

2. ESD test site methodology.

3. ESD test equipment and testing methodology.

4. ESD device and circuit simulation strategy.

5. ESD computer aided design (CAD) design implementation.

6. ESD CAD design rule checking (DRC) tools.

7. ESD CAD design verification tools.

8. ESD design engagement, review, and release process.

9. ESD qualification process [102,103].

10. ESD metrics of devices, circuits, products, technologies, and learning.

11. ESD specifications, targets, and corporate objectives.

12. ESD technology benchmarking, scaling, and continuous learning strategy.

The means at which one carries out these ESD 12 steps can strongly influence the success or failure of a successful ESD design and release process.

9. SUMMARY AND CLOSING COMMENTS

In this Section, an ESD floor plan was established for the rest of the guide. The Section introduced a very brief history of electrostatics, the ESD field, and key inventions and patents that will be discussed. This history, topics, and patents will be referred to in the future Sections. The Section then lays out ESD failure mechanisms on the semiconductor device level, and circuit level, as well as chip level; this forces the reader to start thinking about the nature of failure mechanisms and will be a blueprint for the future discussion. The reader is then exposed to a new way of thinking about ESD. How the ESD design practice is unique? What are the concepts? As the guide unfolds, this blueprint of ESD concepts will be apparent through the examples. The Section then introduced time concepts weaving together the electromagnetic time constants, thermal time constants, ESD pulse time constants, and those of devices, circuits, and systems; this gets the reader thinking in a time domain and what phenomena is important for a given ESD pulse event. The Section then focused on the concept of resistance, capacitance, and inductance, and how things distribute in space and time; this opens the concept of analysis-whether lumped or distributed, and the physical efficiency of the structures, circuits, and systems. Then the question of analysis-how do we simplify the thinking to a simple circuit and current loop? ...and how will that scale? We closed the Section getting the reader to then reduce the thoughts to simple ESD metrics that will be handy for thinking, quantifying, and analyzing. Now the reader is prepared with an ESD mindset to read the rest of the text.

Once you have mastered the ESD thinking of Section 1, the rest is commentary; the reader is now prepared to start sinking into the details, specifics, and examples.

In Section 2, we take a step backwards, and start getting into the practical details; the semiconductor chip ESD architecture is discussed. ESD is both an electrical as well as spatial phenomenon, and hence the architecture and synthesis must reflect both issues. The spatial and electrical connectivity is addressed and how this influences the design and synthesis of ESD networks and floor planning of semiconductor chips.

PROBLEMS

1. Show the time constant hierarchy of the physical time constants on a time axis, for the ESD pulse waveform time constants, MOSFET transit time, bipolar transistor unity current gain cutoff frequency, bipolar transistor unity power gain cutoff frequency, MOSFET circuit gate delay, cross-chip chip interconnect delay time, and package LC time constant.

2. Derive the ratio of the human body model and machine model peak current.

3. Derive the ratio of the machine model (MM) and the cassette model peak current.

Assuming a 200 pF capacitor for the machine model, and a 10 pF capacitor for the cassette model. In both cases, assume a 10 ohm resistor in series with the capacitor source.

4. Derive a relationship between the total energy for a transmission line pulse (TLP) and a very fast-transmission line pulse (VF-TLP), where assume for the TLP trapezoidal waveform a 10 ns rise and fall time, and a 100 ns pulse width, and for the VF-TLP trapezoidal waveform a 1 ns rise and fall time, with a 5 ns pulse width.

5. Calculate the total capacitance and total energy stored in a charged coaxial cable of unit capacitance C per unit length. Assume a typical coaxial cable capacitance, and calculate the total capacitance for a 1, 10, and 100 foot cable. Assuming an initial charging of voltage V, calculate the total charge for the different length cables.

6. For the coaxial cables in Problem 5, assume an initial charging of 100 V, and 1000 V. Assuming a discharge of the cable into a system, calculate the peak current assuming discharging into a 500 ohm resistor.

7. Assuming a 100 foot coaxial cable of capacitance C, convert the coaxial cable waveform into a single capacitor element. What is the source capacitance?

8. Given the ladder network in Section 1, derive the relationship for the Stieljes continued fraction form for the output impedance term z22 (s).

9. Given the ladder network in Section 1, derive the relationship for the impedance parameters z12 (s) and z21(s).

10. Given an ESD diode in the reverse bias mode, we can assume the top electrode has a high resistance and the lower electrode has zero resistance. We can also represent the reverse biased diode as a capacitor element. Assume a ladder network consisting of N resistors on the top electrode, and N capacitors as the rungs of the ladder network, derive the impedance matrix terms.

11. Given an ESD diode in a forward bias mode, we can assume the top electrode has a high resistance and the lower electrode has zero resistance. We can represent the forward biased diode as a conductance term. Assume a ladder network consisting of N resistors on the top electrode, and N conductance terms for the rungs, derive the impedance matrix terms.

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