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In Section 7, we designed the architecture and control algorithm for the LD20 minicomputer-the architecture in terms of functional units, and the control as an ASM chart. In this section, we will sketch the implementation of the LD20 from these starting points. We will not specify each building block and logic equation in detail, because we use the standard methods illustrated in Sections 5 and 6, and you will be able to work out the details with only general guidance.
Good design style dictates that we defer the actual decisions about hardware as long as we can. Up to this point, the design of the LD20 has required us to commit ourselves to only a few specific pieces of hardware. In this section, we will continue to defer hardware decisions until we have dealt with the system on the logical level to the fullest useful extent.
We use the ASM chart extensively to derive the control signals. The ASM chart for the LD20 was shown in Figs. 42, 43, and 44.
PRELIMINARIES
Auxiliary Variables
The ASM chart uses a number of convenient variables that we have constructed from primary signals. The definition of many of these appears in Section 7, but we list them here for reference. In general, the outputs of elements of the architecture are primary signals and do not appear in this list.
Effective address EA: According to Eq. (7-3), the effective address is EA; = MB;- IR4 EA; = IR; (i = 0-4)
Instruction variables: We may most easily form the individual instruction variables as the outputs of a decoder. Technically, they are not auxiliary variables, but it is useful to emphasize their derivation here.
Labels for ASM Chart Locations
These variables are useful parameters for forming output equations and control routings in a systematic manner. The logic equations come immediately from the ASM chart. We have two types of labels: the conditional output terms, which are the basic parameters for expressing the output equations, and the other position markers, not directly associated with conditional outputs but used to label various components of the states of the execute phase.
ASM chart position labels. You should verify each of these equations.
Conditional output terms. Here are a few of these terms. You should verify them and derive the rest.
The most difficult conditional output term to derive is E0.34, at the final exit to FI from the execution of an Operate instruction (see Fig. 38). To assist the synthesis of this equation and the equations for moving from state EO to EO and from state EO to FI, we have defined ASM labels EO.DBL and EO.TST and the auxiliary definition DBL.IS.T. With these judiciously chosen variables, we have
E0.34 = EO.TST-MOREOP
We will encounter EO.TST and EO.DBL again in the development of state transitions.
You should derive the defining equations for EO.DBL and EO. TST, using the ASM in Fig. 44. The exercise will increase your intuitive feeling about implementing the flow of control and also will be excellent practice in manipulating Boolean expressions.
THE DATA-ROUTING SYSTEM
Inputs to the Data Multiplexer
The LD20's 12-bit data path uses 12 multiplexers to control access to the A input of the ALU. In the initial specification, in Fig. 9, we had four sources in the data mux system. As the design progressed, we found that we needed to add MB, MA, and INPUT to the data mux. Looking ahead, we find that the implementation of ALU operations will require that the AC register be available at the ALU's A input, in addition to its position as the sole source of the ALU's B input.
The data path now has eight sources of 12-bit data, a convenient number because 8-input multiplexers are available. However, as good designers we consider the possibility that later we might wish to extend the LD20's basic design to accept additional instructions. New instructions are likely to require additional registers on the main data path. Is there an easy way to leave open an input to the data multiplexers, to allow for such a possibility? Yes: We choose to combine INPUT and EA into a single data multiplexer input, thereby reducing to 7 the data mux inputs committed to our basic design. In the treatment of the input-output interface in Section 9, you will see that the INPUT lines from the external device are required to have three-state control. Data is presented on these lines only when required by an appropriate IOT instruction. On the other hand, EA is used only in ASM state F3. If we use three-state control on the 12 bits of EA, we may create a "minibus" consisting of INPUT and EA. This minibus will use only a single input on the data multiplexer system. INPUT's access to this data mux input is controlled by the IOT protocol. The signal to control the three-state outputs of EA is:
SELEA == F3.1
Although we may use AND gates for the first 5 bits of EA, we find it convenient to use three-state multiplexers for these bits and three-state buffers for the remaining bits, as shown in Fig. 1.
Fig. 1 A three-state implementation of EA.
The Select Signals of the Data Multiplexer
In our final design the data multiplexer system has seven 12-bit sources: AC, MA, MB, MEM, PC, SR, and the combined INPUT/EA. A set of twelve 8 input multiplexers such as the 74LS151 will provide efficient control of these inputs. The muxes require three select inputs, B4, B2, and Bl. Our task is to develop the logic equations that provide the proper inputs to these three control pins on each mux chip. We first make an assignment of the registers to input positions on the multiplexers. The order is arbitrary; Fig. 2 shows our choice.
For each source register, we may write the contributing state terms from the ASM chart. Remember, we are looking for registers used as a source of data in the chart. Table 1 contains the result. Now we can derive the equations for B4, B2, and Bl.
Fig. 2 Bit slice 4 of the main data-routing system, showing the data multiplexer
and register assignments to the data multiplexer inputs.
TABLE 1 DATA MULTIPLEXER CONTROLS
ALU Operations
Although we have always supposed that we would use the 74LS181 ALU chips as the basis for our ALU, we have done nothing to this point that requires these particular chips. Rather, we specified only that the ALU black box must be able to perform certain logic and arithmetic functions on its inputs. We may carry this generality one step further and develop logic equations for each ALU operation.
A scan of the LD20's ASM chart shows that we require the following operations: INCREMENT, PLUS, AND, OR, and NOT. In Section 7, we decided to use the ALU as a source of zeros to clear registers, so the ZERO operation emerges.
Since the AL U also serves as a transparent box for moving data from a source to a destination, the last ALU operation is PASS. Our ALU black box has two sets of 12-bit inputs A and B. The AC feeds into the B input, and the data multiplexer output goes into the A input. We may now tabulate the conditions under which the ALU must perform each operation.
Table 2 shows this information; the logic equations for each ALU operation can be drawn from the presentation.
TABLE 2 -- ALU OPERATIONS
Now at last we specify that the ALU unit contains three 74LS181 Four Bit ALU chips, linked together to perform 12-bit arithmetic. All the chips share 5 control inputs: S3, S2, S1, S0, and M. The least significant chip has a carry in input that we must control, and the most significant chip has a carry-out output, which we may use if necessary. Fig. 3 shows the arrangement, with the proper LD20 logic variables as inputs and outputs. From a TTL data guide, we find the 74LSl81 control input values for our seven arithmetic and logical operations. Table 3 contains the information; 83-80 and Mare T = H, while CIN is T = L. Now, using Tables 8-2 and 8-3, we may write the sum-of-products form of each control input equation:
ALU83
ALU82
ALU81
ALU80
AND + PLUS
E0.10 + EO.11
F AND + ZERO
F1.2 + E0.10 + E0.16 + E0.22 + E1.3 + E4.1 AND + OR + PLUS + ZERO
F1.2 + E0.10 + E0.11 + E0.16 + E0.22 + E0.25 + E1.3 + E4.1 + E5.1
Fig. 3 Implementation of the ALU. The most significant bits are on the left.
TABLE 3 74LS181 ALU CONTROL INPUTS
ALUM NOT + ZERO F1.2 + E0.16 + E0.20 + EO.22 + El.3 + E4.1
ALUCIN = INCREMENT + AND F2 + F4.2 + EO.7 + E0.1O + E0.12 + E0.18 + E0.24 + E1.2 + E1.4 + E2.1 + E3.1
Register-Load Signals
The output of the ALU serves as the 12-bit data bus ALUBUS that connects to the input of several of the registers. We need equations to specify when each register should load the ALUBUS data. Such loading activity shows up in the ASM charts as a register-transfer notation of the form "~ register". We may read the relevant terms for each register load from the ASM charts. Of the five equations-for MA(LD) , MB(LD), PC(LD), IR(LD), and AC(LD)-we show two below. You should develop the remaining ones.
IR(LD) = Fl.2 + F3.2 + EO.5 AC(LD) = EO.6 + EO.1O + EO.11 + EO.16 + EO.20 + EO.22 + E0.24 + E0.25 + El.3 + E4.1 + E5.1
We will implement four of the registers (MA, MB, PC, and IR) with enabled D-register chips. The 74LS378 Six-Bit Enabled D-Register and 74LS379 Four Bit Enabled D-Register are good choices. (The 74LS378 presents its outputs with one voltage polarity; the 74LS379 provides both voltage polarities for its outputs.) These registers have a load enable input, so the register load equations derived above apply directly to the enable inputs of these registers. The AC register must also serve as a shift register to implement the rotate micro-operation.
The shift register building block, with responsibilities for shifting left, shifting right, loading, and holding data unchanged, is more complex to control than is the simple enabled D register. If we choose the 74LS194 as our shifter, two control lines SI and SO govern the operations. The serial inputs for left and right shifts must come from the LINK bit, since the PDP-8 rotate operations treat the AC and LINK as a combined 13-bit circular register. In Fig. 4 we show the structure of the AC circuit. Table 4 contains the relationship of accumulator controls to the ASM chart logic. Let ACS] and ACSO be the LD20 signals that control the S] and SO inputs. Then the logic equations follow from the table:
ACSO = LOAD + RIGHT
= AC(LD) + E0.29
ACS] = LOAD + LEFT
= AC(LD) + E0.28
Fig. 4 Implementation of the AC accumulator and shift register.
TABLE 4 ACCUMULATOR CONTROLS
Architecture and Control of the Link Bit
Fig. 5 Circuit for the link bit.
TABLE 5 -- MULTIPLEXER CONTROLS FOR LINK
The PDP-8 uses the link bit in several ways. There are specific instructions to clear and complement the link. Overflows from arithmetic operations cause LINK to be complemented. The rotate micro-operations in the Operate instruction use the combined AC-LINK as a 13-bit circular register.
We could use a JK flip-flop for LINK storage, and derive the control equations for setting and clearing the flip-flop from the ASM chart. Since there are so many different operations on LINK, we look for a more orderly way to proceed. Suppose that we implement LINK as a simple data storage element such as a D flip-flop. What is the input to LINK in each of the necessary operations? For clearing and complementing, the inputs are zero and LINK, respectively. For left rotates, ACO is the input to LINK, and for right rotates, ACII. Is this all? If we use a D flip-flop, we must also provide for the frequent occasions when nothing happens to LINK. The "do-nothing" situation requires that the input to LINK be LINK itself. If an enabled D flip-flop were available, we could use the enable feature to manage the constructive actions, leaving the flip-flop disabled during the do-nothing periods. However, such individual enabled D flip-flops are not common, so we choose to implement LINK with a simple D flip-flop. Therefore, at all times we must select one of the five inputs to the link register: LINK, LINK, zero, ACO, or ACII. That magic word select shows us the way: use the multiplexer building block. We dodged the link architecture in Section 7 because at that time we did not understand the complete role of the link bit. Now that we know what is required, we can add a LINK circuit to our architecture. We need a 5-input multiplexer, but an 8-input mux is the smallest useful and commonly available chip. Choose a 74LS151; we will control its three select inputs with LD20 signals LINKMB4, LINKMB2, and LINKMBI. Fig. 5 shows the link unit. Table 5 is a summary of the control conditions for the link multiplexer. The resulting equations for the control inputs are:
LINKMB4 = CLEAR
= EO.8 + EO.17
LINKMB2 = SHIFT.RIGHT + SHIFT.LEFT
= EO.28 + E0.29 LINKMBl = SHIFT.RIGHT + COMPLEMENT
= EO.21 + EO.29 + E0.37 + E0.38
STATE SEQUENCING SYSTEM
The State Generator
To produce the proper sequence of states, we will use the multiplexer table lookup technique. There are fourteen states in the LD20's ASM, so 16-input multiplexer chips are suitable. Four 16-input control multiplexers will provide inputs to the four state flip-flops. The 4 flip-flop outputs specify a 4-bit code for the current state. This code serves as the select input to each of the four control muxes. The state generator's architecture is illustrated in Fig. 6, which shows one of the four state-variable circuits.
Fig. 6 Implementation of one of the four state variables.
The state decoder. The encoded form of the current state is fine for driving the control muxes, which require an encoded select input, but the output terms in the ASM require individual signals for each state. To provide these, we decode the state code using a decoder building block. Since we have fourteen states, we choose the 74154 Four-Line-to-Sixteen-Line Decoder.
State assignment and state transitions. With the multiplexer implementation of a synchronous ASM, we have little reason to favor one state assignment over another. An orderly and easily remembered assignment is IDLE = 00002 , Fl through F7 = 00012 through 01112 (18 through 78 ), and EO through E5 = 10002 through 11012 (108 through 158 ), Using this assignment and the ASM charts, Table 6 shows the conditions for state transitions. Whenever it is profitable, we use conditional output terms, since we must implement them anyway to provide the appropriate output signals.
There are two unused states, with assignments 11102 and 11112 • If for any reason the machine is in either of these states, we wish to go next to the IDLE state. Also, for any state, an asynchronous RESET* signal from the control panel must force an immediate (unclocked) jump to IDLE. This apocalyptic master reset is the only asynchronous state change in the design. The 74LS175 Quad D Register that serves as our state-variable memory has an asynchronous clear input. Therefore, if we choose positive logic (T = H) for the state variables, we may use this clearing feature with input RESET* to force the LD20 immediately to IDLE (00002). Although in general we are wary of asynchronous circuit elements, the feature is convenient here.
State multiplexer inputs. Using Table 6, we may derive the inputs to the four state multiplexers, such as the one shown in Fig. 6. Here is a selection of the input equations; you should verify them and derive the remainder.
MUXA.EO = MUXA(8) = EO.9 + EO.12 + EO.13 + EO.14 + EO.15 + EO.3l·ION·IOF + E0.32 + E0.33 + E0.34 + E0.35
MUXB.Fl = MUXB(1) = Fl.l
MUXC.F5 = MUXC(5) = CC + CC = T
MUXC.El = MUXC(9) = F
MUXD.El = MUXD(9) = CC + El.IR·ISZ
MUXD.E4 = MUXD(12) = T
TABLE 6 STATE TRANSITIONS IN THE LD20
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