AMAZON multi-meters discounts AMAZON oscilloscope discounts
SPECIAL SYSTEMS
Priority Control in the Operate Instruction
Perhaps the most sophisticated aspect of the LD20's design is the priority system for the Operate instruction. We must develop logic equations for controlling the priority-level memory element RQSTI-RQST4 and the double-shift flag DOUBLE, and deriving the value of the Operate priority looping variable MOREOP. Table 7 is a summary of the priority assignments for the PDP-81's Operate instruction and the instruction register's bit patterns for the Operate micro operations. From this table we derive logic equations for each priority level PRIl-PRI4:
PRIl = IR3 ° (IR4 + IR5) + IR3 o(IR5 + IR6 + IR7 + IR8)
PRI2 = IR3 o(IR6 + IR7) + IR3 o IR4
PRI3 = IR3 0 IRll + IR3 o(IR9 + IRIO)
PRI4 = IR3 ° (IR8 IR9)
Once the LD20's IR is loaded, these equations establish the priority levels requested by the Operate instruction.
TABLE 7 PRIORITY ASSIGNMENTS FOR THE PDP-81'S OPERATE INSTRUCTION
Controlling the priority flip-flops. The priority flip-flops designate those priority levels of the Operate instruction not yet acted upon. The priority flip flops RQSTI-RQST4 are initialized in state F3 at ASM term F3.1. According to the ASM chart of the Operate instruction, Fig. 44, RQSTl, RQST2, and RQST3 are cleared in state EO at ASM terms EO.19, EO.23, and EO.27, respectively; RQFF4 does not require clearing in state EO. We may use JK flip-flops for RQSTi. We have the following equations for controlling the priority flip-flops:
RQSTl(SET) = F3.1 opRIl
RQST2(SET) = F3.1 opRI2
RQST3(SET) = F3.I·PRI3
RQST4(SET) = F3.I·PRI4
RQSTI(CLR) = F3.I·PRIJ + E0.19
RQST2(CLR) = F3.I·PRI2 + E0.23
RQST3(CLR) = F3.I·PRI3 + E0.27
RQST4(CLR) = F3.I·PRI4
The double-rotate flag DOUBLE. We implement DOUBLE with a JK flip-flop, which requires set and clear control inputs. In F3.1, DOUBLE receives the value of bit IRIO of the instruction register; term EO.30 resets DOUBLE to F. The equations are
DOUBLE(SET) = F3.IeIRIO
DOUBLE(CLR) = F3.IeIRIO + E0.30
Using our mixed-logic notations for the JK flip-flop, we may use either J or K as the set input for DOUBLE, adopting the most convenient voltage polarities for the set and clear terms above.
The MOREOP loop test variable. Look now at the MOREOP test at the bottom of the Operate instruction's ASM in Fig. 44. MOREOP is a derived variable that specifies when it is necessary to return to state EO to process another priority level of the Operate instruction. How is the value of MOREOP related to the condition of the request flip-flops? MOREOP must be true if and only if there is at least one more priority level to process. In any pass through the MOREOP test, the request flip-flop presently being honored is still true, since it will not be reset until the end of the current EO state. Thus MOREOP must be true whenever two or more request flip-flops are true. Table 8 explicitly displays this relation.
Once again we have several possible implementations. Using SSI gates to derive MOREOP is straightforward but messy. Another implementation of this "two-or-more-of-four" circuit is to use a 16-input multiplexer with MOREOP as its output. RQST1, RQST2, RQST3, and RQST4 serve as select inputs to the mux, and each data input is permanently true or permanently false, according to Table 8.
We obtain a more compact implementation using an 8-input multiplexer, again with MOREOP as its output. Look at Table 8 and view the data as arranged, not in sixteen rows but in eight groups of 2 rows each, based on the values of RQST1, RQST2, and RQST3. The two entries for each pair are distinguished by the value of RQST4, and the entries for each pair have outputs that behave in one of three ways:
a. Both outputs are true;
b. Both outputs are false; or
c. The outputs have the same value as RQST4.
TABLE 8 MORE OP AS A TWO-OR-MORE-OF FOUR IMPLEMENTER
This leads us to the elegant implementation of MOREOP shown in Fig. 7. If by now you suspect that the multiplexer is a flexible and powerful building block, you are quite right.
Fig. 7 Implementation of MOREOP.
The IOP Signal Enabler
In Section 7, we developed a shift register architecture for issuing the IOP signals for the IOT instruction. To select the proper time for enabling each IOP signal, we have outputs IOP1.EN, IOP2.EN, and lOP4.EN from the shift register.
The equations for issuing each IOP signal are
IOP1 = IOP1.EN-IR11
IOP2 = IOP2.EN-IR10
IOP4 = IOP4.EN-IR9
State E5 tests the signal IOP4.EN to see if the third pass through the IOT states is in progress. If IOP4.EN is true at that time, the execution of the instruction is complete and the next state will be F1; otherwise, the next state will again be EO.
We select a 74LS194 Four-Bit Universal Shift Register as the IOP enabler.
This chip has two control inputs SI and SO. Table 9 shows the conditions for each operation required of the IOP enabler. We may immediately develop logic variables IOPSI and IOPSO to control the 74LS194's SI and SO inputs:
IOPS0 = LOAD + RIGHT. SHIFT = F1 + E0.31
IOPS1 = LOAD + LEFT.SHIFT = F1
TABLE 9 IOP ENABLE CONTROL
Control of the Interrupt System
Sensing an interrupt request. Since an interrupt request signal EXTINT* may arrive at any time, we must synchronize this signal to the system clock to produce the LD20's INTREQ, used in the formation of the auxiliary signal INT. We may synchronize EXT INn with a D flip-flop; the input is EXTINT*, the output is INTREQ.
Interrupt system enable control. The interrupt system's enable flip-flop JNT.EN requires set and clear commands to control its J and K inputs. According to the ASM chart, the equations are
JNT.EN(SET) = E0.32
JNT.EN(CLR) = F1.2 + E08 + E0.33
Forcing the interrupt. State term F1.2 generates an interrupt by forcing a JMS operation code into the first 3 bits of the instruction register, so that the execute phase will proceed as if it is processing a regular JMS instruction. The MA register is also set to zero at this time to provide the proper effective address for the JMS instruction. The ALU output ALUBUS is the normal data path for input to the instruction register JR. We must add the necessary logic td the inputs of IRa, IRI, and IR2 to create the JMS operation code (1002) in term F1.2, but to pass normal ALUBUS data at other times.
One way to do this is to add a "JMS" (40008) source to the data mux system and select this source into IR during F1.2. However, we are reluctant to use our last, carefully preserved data mux input. But there are only three data bits involved in this transaction. Therefore, rather than enlarging the data muxes to 16-input varieties, we will modify the inputs to instruction register bits IRa, IRI, and IR2 to accommodate the JMS jam at term Fl.2. The equations are
IRa = FI.2o ALUBUSO + FI.2° T = ALUBUSO + FI.2
IRI = FI.2°ALUBUSI + FI.2° F = Fl.2-ALUBUSI
IR2 = FI.2°ALUBUS2 + FI.2° F = Fl.2 0 ALUBUS2
The inputs to bits IR3 through IRII are unchanged by this activity and remain directly connected to the corresponding ALUBUS lines.
The Manual System
MANPULSE. According to our plan, a depression of a manual switch must cause the assertion of a signal MANPULSE for only one clock cycle following the depression. MANPULSE is the output of a single-pulser circuit whose input is MANSW*.
MANEX. In the ASM for the execute phase we use the MANEX flip flop's output to help decide if manual operation or regular instruction processing is appropriate. If you implement MANEX using a JK flip-flop, you should be able to derive the equations for MANEX(SET) and MANEX(CLR) from the ASM charts.
Logic Equations
We have derived some of the logic equations in this section, but have shown actual circuits for only a few. Fig. 8 shows some typical circuits for LD20 logic equations.
Fig. 8 Some typical circuits for logic equations in the LD20.
With your knowledge of mixed logic, you should be able to draft clear and correct circuits for realizing the logic equations needed for controlling the LD20. All the control signals can be constructed with SSI or MSI chips. But don't forget PALs as candidates for creating some of these signals. For instance, several control signals are functions of the bits of the IR: ION, IOF, NOMEM, the Operate instruction priorities PRI1-PRI4, and so on. Perhaps many or all of these signals can be generated by a suitable PAL, with fewer chips.
THE MEMORY SYSTEM
Access to the LD20's Memory
Read and write signals. In the LD20, START.READ and START. WRITE initiate memory reads and writes, according to the memory protocol developed in Section 7. From the ASM, we may derive the equations for these variables: START.READ = F2 + F3.3 + F6.1
START. WRITE = F4.2 + E0.9 + E0.12 + E0.13 + E0.14
The L020's memory interface. The LD20 signals that interface with the memory control unit appear in Fig. 16. The correspondence between the standard memory unit signals and our LD20 variables is
BEGIN.READ
BEGIN. WRITE
MEM.BUSY
ADDRESSi
DATA.INi
DATA. o UTi
= START.READ
= START.WRITE
= BUSY
=MAi
=MBi
=MEMi
EXTERNAL.CLOCK = SYSCLK
The LD20 can supply all these inputs directly from signals available in its architecture or control circuits. Data from the memory unit also goes directly into the LD20's architecture. The remaining LD20 signal from the memory control unit, BUSY, does not appear directly in our LD20 ASM charts. To achieve a compact ASM representation of LD20 memory reads and writes, we introduced in Section 7 a signal CC (Cycle Complete), which has the property of becoming false when a memory read or write begins, and becoming true one clock cycle after the BUSY signal from the memory controller becomes false. We must fabricate this LD20 extension to the standard memory controller. If we use a D flip-flop for CC, we may most readily specify the input CC(D) by describing when CC(D) is false:
CC(D) = BUSY+ START.READ + START. WRITE
CC(D) must be false whenever BUSY is true, or whenever we are about to begin a read or write (i.e., when START.READ or START. WRITE is true). This assures that the output CC is false during the first clock cycle of the memory operation, because either START.READ or START. WRITE was true when the clock pulse that began the memory operation arrived. After that, CC remains false during all remaining cycles in which the memory operation is in progress, because BUSY is true. BUSY will not become false until the first clock pulse after the memory operation is finished; the output CC will not respond to the change in BUSY until the following clock pulse. Fig. 9 shows this circuit.
Fig. 9 Extension of the standard memory interface of the LD20.
The Memory Unit
It is now time to specify the memory chips we wish to use and to design the control unit to use these memory chips in conformity with the protocol developed in Section 7. The memory unit has the following responsibilities: (a) Use the 12 input address lines to access the proper word in the memory.
(b) Perform a write operation upon command, using the information on the data input lines.
(c) Perform a read operation upon command, and maintain the information on the data output lines thereafter, until another memory operation commences.
(d) Provide a timing signal BUSY to indicate to the user when the memory unit is occupied with a user-originated read or write operation.
We have chosen the 6147 4K x 1 Static RAM as the building block for the LD20 memory. Here is a brief description of its characteristics.
The 6147 memory chip. The 6147 is a 4K x 1 static RAM having 12 address pins, 1 data input pin, 1 three-state data output pin, a write control pin, and a chip-enable pin. The write control and chip enable pins are low-active; the rest are high-active. The data-out line is in its high-impedance state during write operations and whenever chip enable is false.
We will use a version of the 6147 having a 70-nsec cycle time: the minimum read and write cycles require 70 nsec. The maximum guaranteed read access time is 70 nsec. Since our design will stabilize the address, chip enable, and input data signals at about the same time (shortly after the initiating clock pulse), we can simplify the rather complex timings for read and write. There are no additional critical timings for the read operation. For the write operation, the address-write-setup time (time that the address lines must be stable before making the write signal true) is 0, the address-hold time (time that the address must be stable after write becomes false) is 15 nsec, and the data-hold time (time that the data must be stable after write becomes false) is 10 nsec.
Memory organization and addressing. The LD20 requires 4096 words of 12 bits. We will use twelve 6147 RAM chips, one for each bit. The RAM chips will be controlled identically.
Memory timing. The 6147 memory chip has no mechanism to announce when its operations are complete. We must determine the guaranteed upper limits of its timing from the data sheet, and we must establish our own means of providing the proper intervals for its operation. In the discussion above, you saw that with stable inputs our major timing constraint is the memory cycle time, which is 70 nsec. How can we produce a signal that reflects the memory cycle time? Perhaps the simplest way is to use a single-shot, for instance the 96L02 Dual Single Shot discussed in Section 4. With the proper combination of external resistor and capacitor, the single-shot will produce a true output for the required time whenever it receives a triggering signal. Call the single-shot output TIMER. Since the single-shot is an asynchronous edge-triggered device, we must be careful in our design to avoid spurious edges (glitches) on the single-shot inputs.
We must now consider how to use this TIMER signal in our memory control unit.
The busy status signal. The memory protocol defines MEM.BUSY as a signal that changes synchronously with the external clock signal. By the nature of the protocol, a memory operation begins synchronous with the clock, so MEM.BUSYand its LD20 counterpart BUSY become true after a clock edge.
Since the termination of a memory operation is an event that is asynchronous to the external clock, we deduce that we will need a synchronizing element to produce a valid MEM.BUSY signal. We have three sources of control of this element-the BEGIN.READ and BEGIN. WRITE inputs and the internal signal TIMER, which indicates the completion of a memory operation. A controlled (JK) flip-flop is the proper building block; we will use two, one to control read and one to control write, each clocked by the input signal EXTERNAL. CLOCK. The input equations for the read-control flip-flop are
READ.BUSY(SET) = BEGIN.READ
READ.BUSY(CLEAR) = TIMER
The flip-flop's output is READ.BUSY. The circuit for the write-control flip-flop is similar, with output WRITE.BUSY. MEM.BUSY is the OR of these two out puts:
MEM.BUSY = READ.BUSY + WRITE.BUSY
You can see this structure in Fig. 10, which shows the entire memory control circuit.
We must investigate the behavior of the flip-flop outputs to verify that they do indeed represent the synchronized busy conditions for read and write operations.
Table 10 is a summary of the READ.BUSY flip-flop's output during the sequence of operations dictated by the memory protocol. Under the legitimate input conditions we see that the circuit performs correctly. There is an equivalent formulation for WRITE.BUSY.
MEM.BUSY is a clean signal, composed of the OR of the output of two flip-flops, only one of which will be changing at any time. Since MEM.BUSY is free of glitches, we may confidently use it to trigger the TIMER single-shot used to time the memory operations.
Fig. 10 A memory control circuit for a 6147 RAM.
TABLE 10 BEHAVIOR OF THE READ.BUSY SIGNAL UNDER THE MEMORY PROTOCOL
The WRITE signal. The 6147 has a low-active control pin for write; the memory chips will be in the read mode whenever we are not writing. The only time we wish to send a write signal to the memory is when WRITE.BUSY is true. We may use the WRITE.BUSY flip-flop's output as a source of the 6147 WRITE input. The address setup time is 0, but the hold times require that we release the 6147's write signal at least 15 nsec before any changes in address or input data. Fifteen nsec is on the order of one 74LS gate delay-much shorter than our LD20 clock cycle. The memory protocol for our LD20 assures that the LD20 ASM will remain in its read or write loop for one full clock cycle after the single-shot timer has forced CC to become true. Thus if we control the 6147's write signal with the single-shot timer, we are assured of an ample hold time. As shown in Fig. 10, the 6147's write signal is true whenever TIMER is true and we are performing a write operation.
This completes the design and implementation of the memory control unit of the LD20. In Fig. 11 we show the timings of the events in a typical memory read sequence of the LD20.
Fig. 11 Timing of a typical memory read operation of the LD20, beginning at
state F6.
FINISHED!
The specification of the LD20 is complete. The implementation of this section was easier and more mechanical than the design of architecture and control in Section 7. This is typical of good design. Because of the care and work put into the abstract design, the implementation is straightforward. When we have drafted the remaining circuit diagrams, and added pin numbers, chip locations, and so on, to each element, we will be ready to commence actual construction.
The LD20 is a real computer. Many people have constructed their own LD20 (or one of its predecessors), and it really works.
Designing the LD20 was a major project. In the course of the design, you have learned in considerable detail how a typical computer is organized, how data flows among its components, and how the control system provides for orderly processing of instructions. Most important, you have had a chance to observe the design process in its entirety. It would be wrong to think that designing the LD20 is easy or obvious. It is neither. Much thought and work went into its structure. So do not be overconfident of your abilities but conversely, do not be dismayed if you cannot produce a quick solution of a complex problem.
The main theme of this guide is that by adhering to good top-down design methodologies-good style-you can deal with the inherent complexity of a problem at the abstract logical level, where it is easier to manage, without creating additional complexities and restrictions by the premature introduction of hardware.
Only when you have mastered the problem at the abstract level should you introduce the hardware.
In order to use the LD20 fully as a real PDP-8 emulator, we must now consider how to interface peripheral devices to the computer. We examine this problem in Section 9.
READINGS AND SOURCES
KUCK, DAVID J., The Structure of Computers and Computations, Vol. 1. John Wiley & Sons, New York, 1978.
MANO, M. MORRIS, Computer System Architecture, 2nd ed. Prentice-Hall, Englewood Cliffs, N.J., 1982.
PDP8/1 and PDP8/L Small Computer Handbook. Digital Equipment Corp., Maynard, Mass., 1972. User's manual for the PDP-8I minicomputer.
PROSSER, FRANKLIN, and ROBERT WEHRMEISTER, C421-C422 Advanced Computer Organization Laboratory Manual. Computer Science Department, Indiana University, Bloomington, Ind. 47405, 1985. Laboratory manual to support the construction, debugging, and study of the LD20 and LD30 implementations of the PDP-81. The laboratory project uses the Logic Engine Development System, manufactured by Logic Design, Inc. Ask the authors of this guide for information.
EXERCISES
1. Why do we sometimes define auxiliary variables for use in the ASM chart?
2. Verify the logic equations for the position labels in the LD20's ASM chart. Pay particular attention to the derivation of EO.DBL and EO.TST.
3. Verify the logic equations for the LD20 ASM conditional output terms given in the text. Derive the remaining terms.
4. Derive the equation for E0.34 directly from Fig. 44, without using the auxiliary variables EO.DBL, EO.TST, or DBL.IS.T.
5. The equations for the data multiplexer select control signals B4, B2, and Bi depend on the mux input position assigned to each register. Although the assignment is a designer's choice, some choices may result in simpler implementation logic than others. Show that the register attached to mux position 0 does not enter into any of the sum-of-product equations for B4, B2, or B1. Is the register used in position o in the LD20 the optimal choice? If not, which register is optimal?
6. Suppose we elect to assign sources to the 8 data mux inputs in the following order: AC, MA, MEM, PC, EA, SR, MB, INPUT. Derive appropriate logic equations for the data mux select controls B4, B2, and B1. Does such an assignment change any other equations in the LD20?
7. In Fig. 1, the instruction register IR is not an input to the data mux. Why?
8. Suppose the multiplexers in the main data path were replaced with three-state circuits to control access to the ALU. We then would have three-state output enable signals on each register: AC(OE) , MB(OE) , etc. Draw a circuit diagram of such a data bus, and derive logic equations for each of the output-enable signals.
9. For several paths in the LD20's ASM, no data mux activity is required, yet the main data mux in Fig. 1 is always enabled, and the ALU controls are performing a PASS operation. Examples are in state F5 and conditional term EO.26. What information is present on the ALUBUS at such times? Why is this phenomenon not harmful to the activities of the LD20?
10. Why is MEM not a destination on the ALUBUS?
Why are EA, SR, and INPUT not destinations?
11. In the LD20, the AC forms the B input to the 74LS181 ALU chips, and the data mux output is the A input. Consult a data sheet for the 74LS181, and show why we cannot successfully reverse these two inputs to the ALU.
12. Derive the LD20's logic equations for the 74LS181 ALU control inputs.
13. Table 3 presents the logic for the 74LS181 ALU control inputs, under our assumption that CIN is T = L. Show why this is a wise choice for CIN. (Hint: Consider the expression for the PASS operation in Table 2.)
14. Derive equations for the register load signals MA(LD), MB(LD), and PC(W).
15. Verify Table 4. Derive the accumulator register control inputs ACSi and ACSO.
16. Implement the link bit as a JK flip-flop. Derive logic equations for setting and clearing the link flip-flop. Compare the clarity and compactness of this approach with the method used in the LD20.
17. Verify Table 5. Why do we assign input position 0 on the link mux to the hold condition? Derive logic equations for the link mux select inputs.
18. Implement a one-hot state generator for the LD20. Compare the complexity with that of the multiplexer controller method. What effect must the RESEn signal have on the one-hot system?
19. In Fig. 5, the mux select code is implemented as T = H. What changes would be required in Fig. 5 if the code were: (a) Implemented with T = L? (b) Implemented with the state variables in reverse order; in other words, with SV.A.H going into mux select input D, and so on? Are such variations on Fig. 5 useful or wise?
20. The 74154 Four-Line-to-Sixteen-Line Decoder, used as a state decoder in the LD20, is a large 24-pin chip that requires more power than chips of the low-power Schottky family. Show a circuit for the state decoder with 74LS42 Four-Line-to-Ten-Line Decoder chips, which have 16 pins and require less power.
21. Working directly from the LD20's ASM, derive Table 6.
22. Derive logic equations for all inputs to the state generator multiplexers in the LD20.
23. The 74LS163 Programmable Binary Counter chip can serve as a 4-bit D register with a synchronous clear. Why do we not use this chip to implement the state generator flip-flops, and thereby support a synchronous resetting of the LD20?
24. Show why the variable MOREOP, which controls looping in the LD20 Operate instruction, is a two-or-more-of-four implementer rather than a one-or-more-of four.
25. Show that the Operate instruction variable MOREOP, described in Table 8, has three more implementations equivalent to Fig. 7.
26. Derive equations for the control inputs to the MANEX 74LSI09 flip-flop.
27. The halt flip-flop HALTFF may be implemented with a JK or an enabled D flip flop.
(a) Using a JK flip-flop, write logic equations and draw circuit diagrams for inputs HALTFF(SET) and HALTFF(CLR). (b) Using an enabled D flip-flop, write logic equations and draw circuit diagrams for inputs HALTFF(D) and HALTFF(EN).
28. Draft circuit diagrams for each auxiliary variable in the LD20.
29. Draft circuit diagrams for the LD20 ASM chart's position labels and conditional output terms.
30. Draft circuit diagrams for the LD20 data multiplexer's select inputs, the ALU control inputs, and the register load signals.
31. Draft complete circuit diagrams for the LD20 ALU system in Fig. 2. Show pin numbers.
32. Draft circuit diagrams for the LD20 registers MA, MB, PC, and IR. Show pin numbers.
33. Draft circuit diagrams for the LD20 AC and LINK circuits. Also draft circuits for the control signals for these systems. Show pin numbers.
34. Draft circuit diagrams for the LD20 state generator system, including the instruction decoder. Show pin numbers.
35. Implement each input to the state-generator multiplexers.
36. Suppose the LD20 ASM were implemented with a one-hot state generator, using D-registers. Write logic equations and draw a circuit diagram for the D-inputs to the flip-flops. How will you implement the RESET operations in the ASM?
37. Implement the LD20's multiplexer-based state generator, using PALs. For the inputs to the multiplexers, use the logic equations you developed in earlier exercises.
38. Implement the LD20's one-hot state generator of Exercise 36, using PALs.
39. Draft circuit diagrams for implementing the priority system of the LD20's Operate instruction using MSI-level technology. Include the priority request flip-flops and their inputs,. the DOUBLE flip-flop and its inputs, and the MOREOP function.
40. Show two different implementations of the circuit for the Operate instruction variable DOUBLE, using a 74LSI09 flip-flop. In one, assume that DOUBLE(SET).H and DOUBLE(CLR).L are conveniently available; in the other, assume the availability of DOUBLE(SET).L and DOUBLE(CLR).H.
41. The LD20's SKIP signal may be implemented with a PAL20LlO. With this PAL, you can also implement the intermediate term (AC=O) that appears in the equation for SKIP. (a) The most straightforward implementation with this PAL yields SKIP.L. Show this implementation of SKIP. (b) By producing the inverse of SKIP within the PAL, you can achieve an efficient implementation of SKIP.H. Show this implementation.
42. Using PALs, implement the Operate instruction's priority request system. This can be done, for instance, with a PAL20LlO and a PALl6R4. The PALl6R4 provides four D flip-flops, which can serve as the request flip-flops. The 20L10 can generate the PRI; signals, which are functions only of the bits in the instruction register. (There is room left over in the 29L10 to generate several other auxiliary signals that are functions of the instruction register bits.) You will have to recast the equations in the text for the inputs to the request flip-flops so that they apply to the D flip-flop implementation.
43. Draft circuit diagrams for the LD20 IOP signal enabler. Include the logic for the control inputs.
44. What changes would be required in the LD20 memory unit if 1024 X 1 RAM chips were used instead of 4096 x 1 chips? What if 1024 x 4 RAM chips were used?
45. Why is it necessary that the memory unit's output signal MEM.BUSYbe synchronized with the LD20 clock?
46. Develop and explain a table similar to Table 10 for the behavior of the WRITE.B US Y flip-flop in the memory unit of the LD20.
47. The 96L02 Dual Single Shot has two equivalent and independent sections. Fig. 10 uses only one of these. Devise an alternative memory control circuit that uses both sections of the 96L02 and avoids the necessity of using the OR gate as a part of the sensitive single-shot trigger input.
48. Complete the memory control circuit diagram of Fig. 10. Include pin numbers.
By referring to a data sheet for the 96L02 single shot, estimate values of the single shot timing resistor and capacitor required to produce a delay of 200 nsec.
49. In Exercise 7-34 we proposed a "manual phase" of the LD20's ASM to perform manual pushbutton operations separately from the execute phase. Implement a modification of the LD20 that incorporates this manual phase.
50. To provide console control of the link bit, we wish to modify the LD20 so that manually loading the accumulator (using the LOAD AC pushbutton) will also toggle the link bit. Make this modification, showing any alterations or additions to the LD20's ASM chart, and any alterations or additions to the LD20's logic equations and architecture.
51. Suppose we have decided to add a new PDP-8 instruction to the LD20, as a part of group 3 of the Operate instruction. The new instruction is: if the interrupt request input is true, then skip two instructions and set the link bit true. Show any changes in the LD20's architecture and ASM required by this new micro instruction.
52. The PDP-8E, another model of the PDP-8 minicomputer, has an additional programmer accessible element-a 12-bit MQ (multiplier-quotient) register. The MQ register is manipulated by an extension of the Operate instruction that includes a set of group 3 microinstructions, designated by Operate instruction bits 3 and 11 equal to 1.
Group 3 has three microinstructions, which fall into two priority classes:
Priority 1: CLA (instruction bit 4 is 1)
Priority 2: MQA (instruction bit 5 is 1)
MQL (instruction bit 7 is 1)
The PDP-8E defines these microinstructions as follows:
CLA (Clear accumulator): 0 --? AC
MQL (MQ load): AC --? MQ; 0 --? AC
MQA (MQ into AC): MQ +AC --?AC
In this exercise you will add this set of microinstructions to the LD20. There is one point that makes this modification nontrivial. The PDP-8E manual states that specifying both MQL and MQA in a microinstruction will cause the AC and MQ register contents to be swapped. The defined operations of MQL and MQA will not support this swap (try it!), so you must be artful in your solution. Your task: make suitable modifications to the architecture and ASM of the LD20 to support the group 3 microinstructions.
53. A customer insists that she needs a computer like the LD20 but in which the computer's AND instruction is replaced by a new instruction that performs the customary AND operation and then replaces the contents of the referenced memory location by its one's complement. Show all the modifications to the LD20's architecture and ASM, and implement the modified instruction.
54. Assume you are testing the LD20, with the clock in its manual mode so that you can easily deliver clock pulses and observe the effects on the display panel lights.
The LD20 is in its IDLE state and the Single Instruction Switch is off. The present contents (in octal) of some of the registers are
MA: 1017
IR: 4212
AC: 0013
MB: 2222
SWR: 4444
What is the sequence of states executed by a properly functioning LD20 if you hold down the CONT (Continue) button and issue a sequence of manual clock pulses?
Related Articles -- Top of Page -- Home