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Basic digital-to-analog conversion
This direction of conversion will be discussed first, since ADCs often use embedded DACs in feedback loops.
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FGR. 30 Elementary conversion: (a) weighted current DAC; (b) timed integrator
DAC; (c) current flow with 0111 input; (d) current flow with 1000 input; (e)
integrator ramps up for 15 cycles of clock for input 1111.
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FGR. 31 Dynamic element matching. (a) Each resistor spends half its time
in each current path. (b) Average current of both paths will be identical if
duty cycle is accurately 50 percent. (c) Typical monolithic implementation.
Note clock frequency is arbitrary.
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FGR. 32 Cascading the current dividers of FGR. 31 produces a binary-weighted
series of currents.
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The purpose of a digital-to-analog convertor is to take numerical values and reproduce the continuous waveform that they represent. FGR. 29 shows the major elements of a conventional conversion subsystem, i.e. one in which oversampling is not employed. The jitter in the clock needs to be removed with a VCO or VCXO. Sample values are buffered in a latch and fed to the convertor element which operates on each cycle of the clean clock. The output is then a voltage proportional to the number for at least a part of the sample period. A resampling stage may be found next, in order to remove switching transients, reduce the aperture ratio or allow the use of a convertor which takes a substantial part of the sample period to operate. The resampled waveform is then presented to a reconstruction filter which rejects frequencies above the audio band. This section is primarily concerned with the implementation of the convertor element. There are two main ways of obtaining an analog signal from PCM data. One is to control binary-weighted currents and sum them; the other is to control the length of time a fixed current flows into an integrator. The two methods are contrasted in FGR. 30. They appear simple, but are of no use for audio in these forms because of practical limitations. In FGR. 30(c), the binary code is about to have a major overflow, and all the low-order currents are flowing. In FGR. 30(d), the binary input has increased by one, and only the most significant current flows. This current must equal the sum of all the others plus one. The accuracy must be such that the step size is within the required limits. In this simple four-bit example, if the step size needs to be a rather casual 10 percent accurate, the necessary accuracy is only one part in 160, but for a sixteen-bit system it would become one part in 655 360, or about 2 ppm.
This degree of accuracy is almost impossible to achieve, let alone maintain in the presence of ageing and temperature change.
The integrator-type convertor in this four-bit example is shown in FGR. 30(e); it requires a clock for the counter which allows it to count up to the maximum in less than one sample period. This will be more than sixteen times the sampling rate. However, in a sixteen-bit system, the clock rate would need to be 65 536 times the sampling rate, or about 3GHz. Whilst there may be a market for a CD player which can defrost a chicken, clearly some refinements are necessary to allow either of these convertor types to be used in audio applications.
One method of producing currents of high relative accuracy is dynamic element matching. FGR. 31 shows a current source feeding a pair of nominally equal resistors. The two won’t be the same owing to manufacturing tolerances and drift, and thus the current is only approximately divided between them. A pair of change-over switches places each resistor in series with each output. The average current in each output will then be identical, provided that the duty cycle of the switches is exactly 50 percent. This is readily achieved in a divide-by-two circuit. The accuracy criterion has been transferred from the resistors to the time domain in which accuracy is more readily achieved. Current averaging is performed by a pair of capacitors which don’t need to be of any special quality. By cascading these divide-by-two stages, a binary weighted series of currents can be obtained, as in FGR. 32. In practice, a reduction in the number of stages can be obtained by using a more complex switching arrangement. This generates currents of ratio 1:1:2 by dividing the current into four paths and feeding two of them to one output, as shown in FGR. 33. A major advantage of this approach is that no trimming is needed in manufacture, making it attractive for mass production. Freedom from drift is a further advantage.
To prevent interaction between the stages in weighted-current convertors, the currents must be switched to ground or into the virtual earth by change-over switches. The on-resistance of these switches is a source of error, particularly the MSB, which passes most current. A solution in monolithic convertors is to fabricate switches whose area is proportional to the weighted current, so that the voltage drops of all the switches are the same. The error can then be removed with a suitable offset. The layout of such a device is dominated by the MSB switch since, by definition, it’s as big as all the others put together.
FGR. 33 More complex dynamic element-matching system. Four drive signals
(1, 2, 3, 4) of 25 percent duty cycle close switches of corresponding number.
Two signals (5, 6) have 50 percent duty cycle, resulting in two current shares
going to right-hand output.
Division is thus into 1:1:2.
FGR. 34 Simplified diagram of Sony CX-20017. The high-order and low-order
current sources (IH and IL) and associated timing circuits can be seen. The
necessary integrator is external.
The practical approach to the integrator convertor is shown in FGR. 34 and 35 where two current sources whose ratio is 256:1 are used; the larger is timed by the high byte of the sample and the smaller is timed by the low byte. The necessary clock frequency is reduced by a factor of 256.
FGR. 35 In an integrator convertor, the output level is only stable when
the ramp finishes. An analog switch is necessary to isolate the ramp from subsequent
circuits. The switch can also be used to produce a PAM (pulse amplitude modulated)
signal which has a flatter frequency response than a zero-order-hold (staircase)
signal.
Any inaccuracy in the current ratio will cause one quantizing step in every 256 to be of the wrong size as shown in FGR. 36, but current tracking is easier to achieve in a monolithic device. The integrator capacitor must have low dielectric leakage and relaxation, and the operational amplifier must have low bias current as this will have the same effect as leakage.
The output of the integrator will remain constant once the current sources are turned off, and the resampling switch will be closed during the voltage plateau to produce the pulse amplitude modulated output.
Clearly this device cannot produce a zero-order-hold output without an additional sample-hold stage, so it’s naturally complemented by resampling. Once the output pulse has been gated to the reconstruction filter, the capacitor is discharged with a further switch in preparation for the next conversion. The conversion count must take place in rather less than one sample period to permit the resampling and discharge phases.
A clock frequency of about 20MHz is adequate for a sixteen-bit 48 kHz unit, which permits the ramp to complete in 12.8s, leaving 8s for resampling and reset.
FGR. 36 Imprecise tracking in a dual-slope convertor results in the transfer
function shown here.
FGR. 37 A conventional analog-to-digital subsystem. Following the anti-aliasing
filter there will be a sampling process, which may include a track-hold circuit.
Following quantizing, the number of the quantized level is then converted to
a binary code, typically two's complement.
FGR. 38 The flash convertor. In (a) each quantizing interval has its own
comparator, resulting in waveforms of (b). A priority encoder is necessary
to convert the comparator outputs to a binary code. Shown in (c) is a typical
eight-bit flash convertor primarily intended for video applications.
FGR. 38 (c) Note: RT goes to junction of R2s.
Basic analog-to-digital conversion
A conventional analog-to-digital subsystem is shown in FGR. 37.
Following the anti-aliasing filter there will be a sampling process. Many of the ADCs described here will need a finite time to operate, whereas an instantaneous sample must be taken from the input. The solution is to use a track-hold circuit, which was described in section 7. Following sampling the sample voltage is quantized. The number of the quantized level is then converted to a binary code, typically two's complement. This section is concerned primarily with the implementation of the quantizing step.
The general principle of a quantizer is that different quantized voltages are compared with the unknown analog input until the closest quantized voltage is found. The code corresponding to this becomes the output. The comparisons can be made in turn with the minimal amount of hardware, or simultaneously.
The flash convertor is probably the simplest technique available for PCM and DPCM conversion. The principle is shown in FGR. 38. The threshold voltage of every quantizing interval is provided by a resistor chain which is fed by a reference voltage. This reference voltage can be varied to determine the sensitivity of the input. There is one voltage comparator connected to every reference voltage, and the other input of all of these is connected to the analog input. A comparator can be considered to be a one-bit ADC. The input voltage determines how many of the comparators will have a true output. As one comparator is necessary for each quantizing interval, then, for example, in an eight-bit system there will be 255 binary comparator outputs, and it’s necessary to use a priority encoder to convert these to a binary code. Note that the quantizing stage is asynchronous; comparators change state as and when the variations in the input waveform result in a reference voltage being crossed. Sampling takes place when the comparator outputs are clocked into a subsequent latch. This is an example of quantizing before sampling as was illustrated in FGR. 2. Although the device is simple in principle, it contains a lot of circuitry and can only be practicably implemented on a chip. A sixteen-bit device would need a ridiculous 65 535 comparators, and thus these convertors are not practicable for direct audio conversion, although they will be used to advantage in the DPCM and oversampling convertors described later in this section. The analog signal has to drive a lot of inputs which results in a significant parallel capacitance, and a low-impedance driver is essential to avoid restricting the slewing rate of the input. The extreme speed of a flash convertor is a distinct advantage in oversampling. Because computation of all bits is performed simultaneously, no track-hold circuit is required, and droop is eliminated. FGR. 38 shows a flash convertor chip. Note the resistor ladder and the comparators followed by the priority encoder. The MSB can be selectively inverted so that the device can be used either in offset binary or two's complement mode.
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FGR. 39 Simple ramp ADC compares output of DAC with input. Count is stopped
when DAC output just exceeds input. This method, although potentially accurate,
is much too slow for digital audio.
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FGR. 40 Successive approximation tests each bit in turn, starting with the
most significant. The DAC output is compared with the input. If the DAC output
is below the input ( ) the bit is made 1; if the DAC output is above the input
( ) the bit is made zero.
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FGR. 41 Two drooping track-hold signals (solid and dashed lines) which differ
by one quantizing interval Q are shown here to result in conversions which
are 4Q apart.
Thus droop can destroy the monotonicity of a convertor. Low-level signals (near the midrange of the number system) are especially vulnerable.
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Reduction in component complexity can be achieved by quantizing serially. The most primitive method of generating different quantized voltages is to connect a counter to a DAC as in FGR. 39. The resulting staircase voltage is compared with the input and used to stop the clock to the counter when the DAC output has just exceeded the input. This method is painfully slow, and is not used, as a much faster method exists which is only slightly more complex. Using successive approximation, each bit is tested in turn, starting with the MSB. If the input is greater than half-range, the MSB will be retained and used as a base to test the next bit, which will be retained if the input exceeds three-quarters range and so on. The number of decisions is equal to the number of bits in the word, in contrast to the number of quantizing intervals which was the case in the previous example. A drawback of the successive approximation convertor is that the least significant bits are computed last, when droop is at its worst. FGR. 40 and 41 show that droop can cause a successive approximation convertor to make a significant error under certain circumstances.
Analog-to-digital conversion can also be performed using the dual current-source type DAC principle in a feedback system; the major difference is that the two current sources must work sequentially rather than concurrently. FGR. 42 shows a sixteen-bit application in which the capacitor of the track-hold circuit is also used as the ramp integrator.
The system operates as follows. When the track-hold FET switches off, the capacitor C will be holding the sample voltage. Two currents of ratio 128:1 are capable of discharging the capacitor. Owing to this ratio, the smaller current will be used to determine the seven least significant bits, and the larger current will determine the nine most significant bits. The currents are provided by current sources of ratio 127:1. When both run together, the current produced is 128 times that from the smaller source alone. This approach means that the current can be changed simply by turning off the larger source, rather than by attempting a change-over.
With both current sources enabled, the high-order counter counts up until the capacitor voltage has fallen below the reference of -128Qsupplied to comparator 1. At the next clock edge, the larger current source is turned off. Waiting for the next clock edge is important, because it ensures that the larger source can only run for entire clock periods, which will discharge the integrator by integer multiples of 128Q. The integrator voltage will overshoot the 128Q reference, and the remaining voltage on the integrator will be less than 128Q and will be measured by counting the number of clocks for which the smaller current source runs before the integrator voltage reaches zero. This process is termed residual expansion. The break in the slope of the integrator voltage gives rise to the alternative title of gear-change convertor. Following ramping to ground in the conversion process, the track-hold circuit must settle in time for the next conversion. In this sixteen-bit example, the high-order conversion needs a maximum count of 512, and the low order needs 128: a total of 640. Allowing 25 percent of the sample period for the track-hold circuit to operate, a 48 kHz convertor would need to be clocked at some 40MHz. This is rather faster than the clock needed for the DAC using the same technology.
FGR. 42 Dual-ramp ADC using track-hold capacitor as integrator.
FGR. 43 The four main alternatives to simple PCM conversion are compared
here. Delta modulation is a one-bit case of differential PCM, and conveys the
slope of the signal. The digital output of both can be integrated to give PCM.
- (sigma-delta) is a one-bit case of -DPCM. The application of integrator before
differentiator makes the output true PCM, but tilts the noise floor; hence
these can be referred to as 'noise-shaping' convertors.
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