In this Section we will be looking at circuits found in black and white TV sets, video monitors and microcomputer terminals. Most of these will cover circuit analysis and some troubleshooting tips.
VERTICAL SWEEP SYSTEM (TRANSISTOR) QUASAR TS-481 CHASSIS
The following circuits are used in Quasar B&W TS-481 and several other chassis:
Vertical Oscillator Circuit
The simplified circuit in Fig. 1 illustrates basic operation of the vertical oscillator. When power is applied, positive voltage from C304 drives TR32 into saturation. Any charge on sawformer capacitor C306 is shorted through diode D32 and TR 32 to ground. At this time electrons flow from emitter to base and C304 charges to polarity shown in Fig. 1.
Capacitor C304 charges very quickly and TR32 then cuts off.
The resulting rise of TR 32 collector voltage, coupled to the base of transistor TR 31, drives it into saturation. Note complete vertical oscillator circuit in Fig. 2. TR 31 then provides a discharge path for C304 through the hold control. As C304 slowly discharges (scan time) the base of TR 32 becomes less negative (thus goes more positive), and forward biases TR 32. When TR 32 conducts, TR 31 quickly cuts off, (retrace time)
and the cycle repeats. The free running frequency of the oscillator is slightly lower than the 60 Hz vertical rate and is determined by the hold control. Just before C304 discharges sufficiently to allow TR 32 to conduct, the negative sync pulse at TR 31's base cuts it off and initiates conduction (retrace).
Fig. 1. Transistor type vertical oscillator circuit.
Fig. 2. Vertical oscillator and sawformer.
Sawformer Circuit
During scan time IR 32 is cut off and capacitor C306 charges through the size control at an exponential rate. TR 32 conducts during retrace time and discharges C306. The resulting sawtooth waveform is amplified by the driver and output stages.
Driver and Output Stages
When power is applied, output transistor TR 34 conducts. This provides a path for yoke current from ground to B plus and the beam moves to the top of the screen. In normal operation a charge is accumulated on capacitor C311 and becomes the voltage source for output transistor TR 35 and sawformer capacitor C306. Note driver and vertical output circuit in Fig. 3.
As sawformer C306 charges, driver transistor TR 33 is brought into conduction. Its emitter is direct coupled to the base of output transistor TR 35 and it also conducts. This transistor's dropping collector voltage is coupled to the base of TR 34 and reduces its conduction. Current through the yoke diminishes and the beam moves toward screen center. As the beam moves through screen center, TR 34 cuts off, yoke current reverses, TR 35 conducts more and the beam moves to the bottom of the screen.
Yoke current for the lower portion of the scan is from the negative side of C311, through the yoke, R372 to ground, then back to R322, TR 35 and R 321 to the positive side of C 311.
With the beam at the bottom of the screen, oscillator transistor TR 32 again conducts shorting out the charge on C306. Driver TR 33 and the output TR 35 cuts off and output TR34 again conducts as the beam retraces to the top of the screen.
Fig. 3. Vertical output and driver circuit.
Linearity Correction Circuit
The normal charge-discharge of sawformer capacitor C306 through the resistance of the size control and R325 is at an exponential (non-linear) rate. By injecting a sample of the output (which is the opposite phase) via C313 at the negative end of C306 the two opposite exponential curves, in effect, add together and cancel the non-linearity. Control VR33 provides a means of varying the resistance from C306 to ground and thus alters the waveform produced.
Horizontal AFC Oscillator and Driver Circuits
In the AFC circuit (see Fig. 4) positive and negative sync pulses are applied to series connected diodes. A sawtooth (integrated horizontal pulse from the sweep transformer) is referenced to the horizontal sync.
Any phase (time) difference between them develops a correction voltage that is fed into the base of the TR42 oscillator transistor. Horizontal oscillator and driver circuit operates as follows: Forward bias is applied from B+ to the base of TR42 horizontal oscillator via R406, R412, and R414. Collector current through the primary winding of 1401 induces a positive voltage in the secondary, that is applied to the base through C410.
This positive voltage quickly drives the transistor to saturation and places a charge on C410. With no current change in the primary, the secondary voltage drops and turns off the transistor. The magnetic field then collapses. The transistor remains in cut-off until C410 discharges and forward bias is again applied. This above condition repeats itself at the horizontal rate as determined by IA01, C409 and C410. The output is taken off the emitter of the oscillator transistor TR42 and amplified by the driver transistor TR43. This stage is transformer coupled to the horizontal output transistor TR44.
Horizontal Output Circuit
When the oscillator and driver turn on, the horizontal output cuts off and energy builds in L402. When the driver cuts off, this energy is released and the horizontal output transistor TR44 conducts. Collector current is from ground, through sweep transformer T401, emitter to collector of TR44 and R423 to the B+ supply. This creates a magnetic field in the sweep transformer and yoke, thus moving the beam to the right side of the screen. Note the horizontal sweep circuit in Fig. 5.
A negative going voltage applied to the base of TR44 (from 1402) cuts it off. As the magnetic field in 1401 and yoke collapses a large negative pulse appears at the emitter of TR44 and the beam retraces to the left side of the screen.
A negative 200 volt peak-to-peak pulse appearing at terminal 4 of the sweep transformer 1401 is fed to the AFC circuit. This same point is used to supply positive 19 volts (after rectification) and is divided down to supply and power other circuits in the receiver.
Diode D49 rectifies the positive portion of the pulse (during scan time) and charges capacitor C491. If you have AFC problems check for a shorted diode D49 or C491 capacitor as they may cause this AFC pulse to be missing.
Fig. 4. Horizontal AFC and oscillator.
IF AGC CIRCUITS-QUASAR B&W TV (SOLID-STATE)
The automatic gain control (AGC) system controls the gain of the first IF amplifier to maintain a constant signal at the video detector. AGC is also applied to the RF amplifier under strong signal conditions to prevent signal overload, cross modulation effects, and etc. With no signal, or on very weak station signals, the IF and RF amplifiers are biased for maximum gain. As signal level is increased the AGC system applies more forward bias to the IF amplifier, thereby reducing its gain.
As signal level increases the IF gain decreases until a pre-determined level is reached. At a given level forward AGC voltage (more positive) is then applied to the RF amplifier to reduce its gain.
Fig. 5. Horizontal sweep output stage.
No Signal Condition
The AGC gate is forward biased by the positive voltage on its base and is normally in conduction. A positive going pulse developed during retrace time is coupled from pin 1 of the sweep transformer to the collector of TR 18 gate transistor through C 182, (.1 µF) and diode D18. Since the gate transistor is in conduction the upper end of C182 is clamped at a low DC level. As a result the high positive retrace pulse charges C182 as shown in Fig. 6. At the end of retrace the positive end of C182 is returned to ground via the sweep transformer pulse windings.
The negative voltage at the upper end of the capacitor reverse biases diode D18. It also opposes the positive voltage appearing at the junction of R186, R185 and CR181. This produces a greater drop across R186 and less forward bias appears at the base of the first IF transistor TR11. This reduction in forward bias optimizes IF stage operation for maximum gain.
The RF amplifier is also biased to produce maximum gain by voltage divider action of resistors R188 and R187.
When a station is tuned in, signals appear at the video detector diode D11. The diode detector recovers video information which is negative at D1 1 and this signal is fed to the first video amplifier transistor which appears on the emitter in the same phase. The emitter is DC coupled to the base of the AGC gate transistor TR18 (see Fig. 7) and this stage is normally in conduction. However, a negative going signal decreases the AGC gate transistor TR18's conduction (when the retrace pulse is present on the collector). With decreased conduction, C182's charge decreases, less negative voltage appears at the junction of C182 and R182 thereby allowing more positive voltage to be fed to TR11, first IF amplifier's base. This increases conduction and the IF gain is reduced.
RF AGC Operation With strong signals, the first IF stage TR11 is conducting harder, collector current increases and a larger voltage drop occurs across the 270 ohm resistor, R105. This drop is coupled into the base of the RF AGC delay transistor TR19. The large voltage drop across R105 appears as a negative going signal to the base of the transistor TR19. As a result it conducts (normally TR19 is cut off) and increases the AGC voltage divider that feeds AGC voltage to the tuner. With weak signals less voltage drop occurs across R105, TR19 transistor is cut off and the RF bias voltage is supplied from voltage divider action of R188 and R187. This action then causes maximum RF gain. From the above information it is now evident that the AGC system functions in a forward bias mode for the IF and RF amplifiers.
SYNC SEPARATOR CIRCUIT (B&W TV SOLID-STATE)
The solid-state sync circuit shown in Fig. 8 consists of the sync separator stage and the sync amplifier stage.
Fig. 6. IF AGC circuit.
Sync Separator Stage
The sync separator removes the negative going sync pulses from the video sync at the base of TR16. During sync time, emitter to base current charges C161 in the polarity shown. During scan time, the charge on C161 keeps TR16 cut-off and effectively removes all other information. The negative sync tips turn transistor TR16 on and the resulting base to emitter current (during pulse time) restores the charge on capacitor C161.
Amplified and inverted sync pulses will then appear at the collector of transistor TR16.
Fig. 7. RF AGC circuit.
Fig. 8. Solid-state sync circuit.
Sync Amplifier Stage
Positive going sync pulses from TR16 are coupled to the base of TR17, sync amplifier stage, via capacitor C171. The sync amplifier transistor TR17 operates split load with positive going sync from the emitter and negative going sync pulses from the collector.
The positive going sync pulses are coupled to the vertical sweep system through an intergrator network (R301, C301, R302, and C302) and then onto the horizontal AGC circuit through C402. Negative going pulses are then coupled to the horizontal AFC circuit through a coupling capacitor not shown in this circuit. When troubleshooting this circuit be on the look-out for leaky coupling capacitors, resistor value changes, and faulty transistors. Use the scope to trace pulses through these two stages.
VIDEO IF CIRCUITS (B&W TV SOLID-STATE)
This IF section consists of three discrete transistor common emitter amplifiers.
As we see in Fig. 9 the first IF amplifier stage is AGC controlled and gain reduction occurs with increased forward bias. The IF signal from the tuner is coupled via a coax cable to the IF input (A3 and A4) terminals on the circuit board. The signal is coupled through a 39.75 MHz upper adjacent video trap, a 47.25 MHz lower adjacent sound trap and a bandpass shaping network to the first IF amplifier transistor TR11.
Base bias for the first IF is supplied from B+ through R186 (4.7K) resistor and in conjunction with the AGC circuit, bias is varied in direct proportion to signal strength. Thermal stability is provided by emitter resistor R113 and it is bypassed to reduce degeneration.
The amplified signal at TR11 (first IF) collector is coupled through L104 and C113 to the base of the second IF transistor TR12. A 41.25 MHz trap at this point attenuates the sound carrier to establish a 10 to 1 ratio of video to sound carrier gain for proper intercarrier sound operation. The amplified signal at the collector is coupled through L106 and C115 to the base of transistor TR13, third IF stage.
Base bias, on TR13, is established by R111 and R112. Capacitor C117 (4 pF) from the bottom of the collector coil to TR14 base couples an out of phase signal (180 degrees) that cancels out the signal fed back internally from collector to the base due to junction capacitance. The amplified output of this stage is coupled into the video detector through a capacitive network.
Capacitors C119, C120 and C121 resonate the coils in the third IF collector and detector circuits. Capacitors C119 and C121 also provide coupling between the two stages.
Fig. 9.Transistor video lF system.
AUDIO SYSTEM (IC SOLID-STATE)
In this system the sound IF signal (4.5 MHz FM) is coupled from the first video amplifier's emitter to the audio IC via transformer L201 as shown in Fig. 10.
The first section of the IC provides both gain and limiting of the 4.5 MHz signal. The FM detector within the IC receives two 4.5 MHz signals from the limiter. One is applied directly to the detector, the other is shifted in phase by quadrature coil L202 (external) and returned to the detector. Frequency modulation of the IF signal produces a phase difference (from 90 degrees) of the two signals reaching the detector and results man output that corresponds to the original audio at the TV station.
The recovered audio signal appears at terminal 8 of the IC and is coupled via C501 to the last IC section for low-level audio amplification. Control VR51 adjusts the DC bias of the FM detector output stages to vary the volume.
Output of the IC is fed to the audio output stage TR53, a class A amplifier. Emitter to base bias for output transistor TR53, is set by the DC level from the IC. Resistors R503 and R508 provide thermal stability and current limiting. Capacitor C506 prevents degeneration of low frequencies across R503. Transformer 1501 matches transistor TR53 to the 8 ohm speaker. A VDR across the transformer protects transistor TR53 from high inductive kicks due to transients.
HORIZONTAL OSCILLATOR AND DRIVER (SOLID-STATE)
Forward bias is fed from B+ to the base of TR42 horizontal oscillator (See Fig. 11) through R406, R412 and R414. Collector current through the primary winding of L401 induces a positive voltage in the secondary, that is applied to the base through C410. This positive voltage quickly drives the transistor to saturation and places a charge on C410. With no current change in the primary, the secondary voltage drops and turns off the transistor. The transistor will remain in cut-off until C470 discharges and forward bias is again applied. The output is taken off the emitter of TR42 and amplified by the driver transistor TR43. The oscillator and driver stages conduct together.
Fig. 10. Audio system - IC type.
Fig. 11 Horizontal oscillator and driver circuit.
POWER SUPPLY CIRCUIT (SOUD-STATE REGULATED)
This regulated power supply circuit is found in many solid-state black and white video monitors or terminals. The complete power supply circuit is shown in Fig. 12.
Depending on monitor screen size and B+ voltage requirements along with the AC line voltage, the HI/LO T401 transformer secondary tap switch SW403, is used for nominal unregulated DC voltage from the full-wave bridge so that it may be maintained at about 23 volts for regulator efficiency. Set the SW403 HI/LO switch as follows: The low position should be selected for line voltages of 90-110 (or 180-220) volts AC and the high setting for 105-132 (or 210-164) volts AC.
The 115/230 volts AC switch, SW402, provides a series or parallel connection of two identical primary transformer windings for American or European AC line voltage sources.
A diode bridge rectifier unit is used to provide 23 volts of unregulated DC to the B+ regulator circuits. The main regulated B+ supply is generated or controlled by a series pass regulator transistor Q401 and R401 resistor driven by an error amplifier transistor Q403. An adjustable sample of the output B+ voltage is compared to the Zener reference voltage.
POWER SUPPLY SERVICE TIPS (REGULATED)
The most common problems in this type of power supply are faulty rectifier diodes, Zener diodes, regulator transistors and filter capacitors.
A shorted bridge rectifier diode will open fuse F402 and an open diode will lower the B+ voltage and may produce a hum bar on the monitors screen.
A short in the regulator transistors or filter capacitor C405B will blow the F403 fuse. Of course, any short up stream on the B+ line will also blow this fuse. If you find no regulation of B+ at all, suspect the pass transistor Q401, R401, Q402, Q403 and the Zener diodes. An open C405A or B will cause reduced B+ voltage, hum bars and picture pulling. It may also cause picture rolling and weaving. An open R401, 25 ohm at 20 watt resistor, will cause complete loss of the 14 volt regulated B+ voltage.
Fig. 12. Regulated power supply circuit.
HORIZONTAL OSCILLATOR (SOLID-STATE IC)
This circuit is used in black and white video monitors and display terminals for computer read-outs.
Circuit Description
The horizontal oscillator and its frequency control is accomplished by IC801. Of course, the inner workings of the IC are very complex, but some circuit characteristics are determined by external components. As we dig into this circuit operation follow along with the diagram shown in Fig. 13.
For horizontal frequency control two input signals are compared and a resultant error voltage is fed to the oscillator to hold a frequency that is in sync with the input signal. The first signal is the negative going horizontal sync pulses which are fed to IC801 via R801 and C801.
A second 130 volt P-P feedback pulse from the horizontal sweep system is coupled via R810 to an integrating network. Resistor R912 provides a means of slightly shifting the reference sawtooth signal. This provides a method of shifting the raster for the best static relationship between the incoming sync and screen center.
The sync input pulse at pin 3 causes a sampling of the reference sawtooth voltage at pin 4 and the timing relationship will determine what DC voltage is developed when the sample occurs at the zero crossing of the sawtooth when no error voltage is developed and the input and oscillator are in sync. As timing varies an error signal is developed and fed to the external circuit at pin 5.
The oscillator time constant is determined by a thermally stable capacitive resistive network. The R807 pot is the adjustable horizontal hold control. R808 and R812 is an external divider network which controls the relative on/off time for the square-wave drive signal at pin 1.
The error voltage at pin 5 is coupled to the frequency determining network by R804 at pin 7 of the IC. The oscillator is corrected by this input.
Fig. 13. Horizontal oscillator - IC type.
The rate at which correction occurs is very important, especially during vertical retrace. If the horizontal pulses are missing during a portion of the vertical retrace, no error signal is developed and the oscillator will be free running. When the pulses return, and an error voltage is developed, the oscillator will be pulled back to the correct frequency.
Components C802, R802, R803 and C803 provide a time constant to maintain a control voltage during certain periods, such as the vertical retrace, when sync pulses are absent. Problems in this section of the circuit will appear as tearing at the top of the screen. Bending at the top of the screen with certain settings of the horizontal hold control occurs because the natural frequency of the oscillator is different from the sync and time is required to overcome the phase error. This time is dependent on the network time constants described already. For a faster response when using video tape recorders (VTR or VCR), SW801 (the VTR-VCR switch) removes the short across R803 increasing the circuits time constant.
Transformer T801 is required to provide a high current, low voltage drive to Q901, the horizontal output transistor. R814 and C809 decouple the transformer primary so that pulses are not transferred to the power supply, while providing the DC current for Q901. R815 and C808 were selected to reduce ringing in the primary of the driver transformer. Figure 4-14 shows the timing relationship of key voltage and current waveforms that occur during one horizontal scan and retrace cycle.
Troubleshooting Tips
If the oscillator is dead (no horizontal drive signal) check for proper DC voltages at pins of IC801 and the driver transistor Q801. Use the scope to check for a drive signal at the base of Q801. Also, look for a feedback pulse via R810 to pin 4 of the chip. Should the picture not lock-in (horizontally) use your scope to see if the correct sync pulse is at pin 3 of IC801. The most common problems found in these circuits is a faulty IC801, Q801 driver transistor and driver transformer T801.
POWER SUPPLY (B&W TV) AC/BATTERY TYPE
This circuit is found in the Quasar TS-483 B&W TV set that can be used on an AC power line or 12 volt battery. The set has a power transformer and is protected with a 1 amp fuse. The secondary winding provides AC to the full-wave bridge rectifiers. Capacitor C705 filters the 120 cycle ripple of the bridge output voltage. Regulator transistor TR73 regulates the B + voltage at +11.5 volts. The circuit for this power supply is shown in Fig. 15.
Regulator Circuit Description
Transistor TR73 functions as a variable resistance in parallel with R704. Its resistance changes directly with line variations and indirectly with the load.
The regulator circuit reacts so that an increase in output voltage reduces TR73's base bias and conduction, whereas a decrease in output voltage increases base bias and conduction. This results in a relatively constant output voltage with changes in line voltage and/or load variation.
Reference Amp and Driver
Zener diode D75 clamps the emitter of reference amplifier transistor TR71 at 4.8 volts. A sample of the output voltage from the divider network (R701, R702 and control VR71), appears at the base of TR71. If output voltage increases, its conduction decreases and the collector voltage drops (more negative). If the output voltage decreases, conduction increases and the collector voltage rises (less negative). The collector is connected through R708 to the base of driver transistor TR72, an emitter follower. Its emitter connects to the base circuit of regulator transistor TR73.
Charging Circuit
With the set turned off and the AC/Battery switch in the AC position the regulated supply charges the external battery when it is connected.
The power supply operates as described above except that a jumper in the battery plug completes the ground leg.
A section of the on/off switch opens the circuit to the receiver section circuits. Resistor R700 connects from the reference amplifier base circuit to ground through the low resistance of the CRT filament to increase the output voltage for charging. The charging path is from ground through D76 (and D77) and the battery to the B+ output.
Fig. 14. Waveforms for horizontal scan system.
Fig. 15. Low voltage power supply.
Battery Charging Operation
With the AC/Battery switch in the battery position, the negative lead of the battery connects through diodes D76 and D77 to ground. A 2 amp fuse to the positive battery lead protects the battery against overloads.
You can use the troubleshooting procedures given in other sections of this guide for regulated power supply systems.
SOLID-STATE IF SYSTEM (B&W TV)
In this Zenith IF circuit, during a "no signal" condition, the input AGC level is about +4.5 volts at test point "E" (Refer to Fig. 16) to the IF and about +2.0 volts to the tuner, producing a very snowy raster. If no snow is observed on the screen (or at the second detector test point "C" with a scope), remove AGC lead to video IF and insert a variable bias voltage, adjusted to +4.5 volts. If this opens up the IF system and heavy snow is observed, there is an AGC problem: This indicates the tuner and tuner AGC are all functioning normally.
If some weak snow is observed on the raster, with the tuner disconnected, then the IF amplifier stages are OK. If no increase in snow level is observed when the tuner is again connected, then there is tuner trouble: tuner AGC, transistor, or delay circuit. On the other hand, if snow on the raster comes up to normal when the tuner AGC lead is removed, then the trouble is in the tuner AGC delay since the tuner RF amplifier transistor (IR 1) is automatically shifted to full gain with the AGC (delay) lead removed.
Thus, if the RF amplifier is excessively forward biased, (more positive at the base) it is still impossible to remove all snow, when the W amplifiers are good and operating at full gain.
Should no second detector signal be observed at test point "C" after making IF bias tests, then check IF transistor emitter voltages: stages are operating normally when (note Fig. 16) third IF (TR3) is about +3.7 volts, second IF (IR 2) is +2.2 volts and the first IF (IR 1) will be on the order of +4.5 volts. In some chassis, without the AGC tuner delay transistor the first IF emitter will be about +0.7 volt and the AGC output at test point "E" will be +1.5 volts under a "no signal" condition.
VIDEO AMPLIFIER CIRCUITS (ZENITH B&W TV)
The video driver (IR 4) is an emitter-follower, with no gain, matching high impedance of the second detector to the low impedance of video output transistor (IR 6), base. The collector of the video driver delivers composite video via the 0.2212 (C50) and 1K resistor to the base of sync limiter (TRIO) for sync separator action. This video amplifier circuit is shown in the Fig. 17.
The video driver stage may overload and the second detector signal may measure 4 volts peak-to-peak but the output may be compressed or clipped at the 2 volt level. Thus, trouble is indicated in the output circuit.
Check out the bias voltages and the video driver transistor itself.
Fig. 16. Video IF circuit system.
Fig. 17. Video amplifier circuit.
Fig. 18. AGC and noise limiter circuit.
It is possible to remove the Noise Gate Driver (TR 5) action, by grounding the base as a troubleshooting check.
As a service check of the video amplifier system, use a 0.1 uF capacitor at 600 VDC, to pick up the 6.3 VAC from the power transformer at pin 1 located on the CRT socket. This signal can now be used for signal injection to locate faults in the video stages as follows.
• Connect the capacitor through a clip lead to the collector of video output transistor (IR 6), which should now show a little AC hum on the screen of the CRT.
• Next connect the capacitor to the base of TR6, and this will give you an indication of the transistor stage gain on the picture tube screen.
The contrast control will have no effect during this test.
• There should be little change in AC amplitude when moving the capacitor to Test Point "J", at full contrast setting, with a properly operating Noise Gate Driver.
• Similar performance will be observed on the emitter of the Video Driver (TR4). Since the Video Driver is a no-gain device, similar amplitude should be observed on the driver base, test point "C", at the video detector.
ACC CIRCUIT (SOLID-STATE ZENITH B&W TV)
This AGC system is "gated" with keying pulses fed from the horizontal circuit via 0.05 le capacitor (C53). Test point "E" IF AGC varies from +4 to +5 volts at minimum signal to +7 on strong signals.
Tuner AGC varies from +2 volts to +4 volts (strong signal), with transistor tuner delay.
To adjust AGC control R33, (see Fig. 18), place the noise gate pot (R26) counterclockwise at minimum and adjust the AGC control just below the distortion point. Reset R26 just below the point at which picture position is affected.
R26 may also be adjusted with a scope as follows: Composite video sync tips should just be removed so that the stage will respond only to noise pulses exceeding the amplitude of the sync level.
It also is possible to set the AGC level for 2.5 volts peak-to-peak composite video information at test point "J". If AGC action is not correct, make the following checks:
• Short the noise gate (TR11) base to emitter, removing its possible affect on the sync limiter (TRIO) and the AGC gate transistor (TR9).
• It is possible the noise gate pot (R26) is set too high, thus causing sync information to be clipped, and AGC action then occurs "off the video" instead of the sync tips which results in picture pull and roll.
• Watch for a shorted noise gate driver (TR5), emitter to collector.
This will load down test point "J" and cause loss of video at the CRT.
• The AGC gate transistor (TR9) develops a bias proportional to sync tip amplitudes as a gated rectifier. This is fed to the AGC output transistor (TR8) at test point "F" whose emitter is used as follows:
-Through test point "E" as IF AGC to the base of the first IF stage.
-Directly to the emitter of the AGC delay transistor (TR7) and thus to base of the tuner RF amplifier stage.
-A variable bias supply, positive going, may be connected to the emitter of AGC output transistor (TR8) and may be varied through the voltage range of +4 to +8 volts to simulate varying AGC levels, duplicating proper action for both the tuner and IF AGC systems. This is a good technique to use for isolating AGC circuit troubles.
Diode X4 in the base of the AGC gate transistor (TR9) operates as follows:
• Under normal conditions the noise gate transistor (TR11) is biased to saturation, and the collector effectively shorted to ground.
• When the noise gate driver (TR5), in the video circuit, receives a noise pulse, it is amplified and fed to the base of the noise gate transistor (TR11), taking the stage out of saturation, thereby, lifting the collector off ground, which then affects both sync and AGC. The AGC gate transistor (TR9) base bias is changed, causing it to momentarily cease operation for the duration of the noise pulse.
Diode X4 does not permit the sync limiter to go into conduction via the two series 5.6K resistors and contrast control to ground, while the noise gate is out of saturation.
Note that during normal operation, the base bias of the AGC gate transistor (TR9) is determined by the voltage at test point "J", through the two series 5.6K resistors via X4 to "ground" (the noise gate being in saturation or effectively shorted). Diode X3 rectifies the gate pulses from the 0.05 i .L.F capacitor (C53) to get the negative voltage required for the AGC gate transistor (TR9) collector.
Diode X2, between the AGC gate transistor and the AGC output transistor serves to isolate the gate pulses from the AGC output itself.
This 1Y21B55 Zenith B&W chassis uses the gating diodes instead of the AGC delay transistor stage. As we look at this circuit, refer to Fig. 19.
In the AGC output transistor (TR7) emitter circuit, under a weak or "no signal" condition; the voltage, at the base of the first IF transistor (TR1) goes through test point "E" to the junction of diode X3 to the junction of the AGC output transistor (TR7) emitter (and 680 ohms to ground), maintaining the IF AGC bias at about +0.7 volts for full gain.
As the AGC output transistor emitter voltage increases with increased signal level, X3 diode acts as a switch preventing test point "E" from exceeding the predetermined maximum voltage determined by the resistor divider action of R31 and R41.
The tuner RF amplifier is biased at about +2.0 volts, determined by the resistor divider network of the 47K and 5.6K resistors. The way diode X2 is polarized, there can be no effect on the tuner RF amplifier base voltage until the AGC output transistor (TR7) emitter exceeds +2 volts.
This is, however, about the voltage at which the first video IF stage begins to approach a fixed bias on the resistor divider network R41 and R31.
At "no signal", or a very weak signal, the AGC output transistor (TR8) conducts little and the maximum IF gain bias of about +4.5 to 5.0 volts is obtained from the 24 volts supply by divider resistors, with TR8 emitter at the junction of the two. VHF tuner bias is set at about +1.8 to 2.0 volts, at maximum gain, by the tuner resistor divider network. The tuner delay transistor (TR7) does not conduct at low signal levels.
As the input signal increases, the developed voltage at test point "F", base of the AGC output transistor, increases, it conducts more, and its emitter voltage (and the IF AGC through test point "E") rises.
The tuner AGC delay transistor (TR7) emitter is biased at +2 volts, at the junction of R32 and the 15 K resistor between B+ 24 volts and the AGC delay control (R2) to ground. When the IF AGC voltage rises, moving the emitter of the PNP tuner delay transistor (TR7) more positive with respect to the base, TR7 begins to conduct, and the tuner AGC voltage rises. At this signal input level, the IF AGC voltage increase slows down and most of the additional gain reduction is done with an increasing AGC voltage to the tuner from the emitter of TR8, through the delay transistor TR7.
if AGC is not capable, alone, of providing sufficient reduction in gain under strong signal conditions. To provide sufficient reduction, AGC is applied to both the first IF and the VHF tuner when the incoming signal reaches a certain level. By delaying the tuner AGC, maximum performance is assured on weak signals; the tuner delay entry point is determined by how soon the delay transistor TR7 begins to conduct. The AGC delay control sets the base voltage and thus the IF AGC level at which the delay transistor, TR7, conducts.
The delay point is factory set, using R2, so that tuner AGC reads slightly more than +2 volts when input signals are between 1 and 2 millivolts. If R2 is adjusted too low (clockwise), tuner AGC action occurs early, and more snow may appear at low or medium signal levels. If, on the other hand, R2 is set too high (counterclockwise), cross modulation interference may appear under strong signal conditions. A. good com promise may be obtained by setting R2, on a medium signal level, clockwise until a noticeable increase in background snow level occurs then just back off until the snow level decreases. The AGC level control setting of R33 is not affected much by adjustments of the delay control.
Fig. 19. Transistor AGC circuit - gated.
Sync Circuit Operation and Service Tips
The overall performance of the sync limiter (TRIO) can be best checked out with a scope and a LC probe. Composite video will be viewed at the base of (TRIO). Sync information, amplified, will be observed at the collector.
The sync limiter base is biased at -2.1 volts, for clamping and detection action. Clamping occurs on the top of the sync pulses so the average is negative. If no bias is measured, or the base is positive, then the transistor is open, or (C50) is open and not charging. The -2.1 volts at the base indicates normal sync limiter action.
When a noise pulse appears at the noise gate (TR11) base, and the stage moves out of saturation, sync action momentarily ceases for the duration of the pulse, but immediately recovers, as follows.
• A 0.22 uF capacitor (C50) is in series with the base emitter diode junction of the sync limiter transistor (TR10) to ground, under normal conditions of the noise gate (IR 11) in saturation.
• Since the "diode action" of the transistor junction is a one-way gate, the capacitor C50 charges on composite information, creating the average negative value of - 2.1 volts on the sync limiter base.
• The 820 K resistor, off sync limiter base to the 24 volt B+, properly biases the base so that conduction occurs in the middle of the sync tip information.
• When a noise pulse takes the noise gate (TR II) out of saturation, and the sync limiter emitter voltage increases, causing the stage to cease operation, the C50 capacitor loses its charge since composite video information is momentarily not conducting through it in the one-way path.
• After the noise pulse is passed, and the noise gate returns to saturation, the sync limiter, on the next horizontal sync pulse, immediately re-establishes normal operation.
Audio and Sound IF (Solid-State B&W TV)
The solid-state audio system may be checked with a 0.1 µF capacitor from the power transformer on the CRT filament winding. This gives you a 60 Hz test injection signal for circuit troubleshooting.
Troubleshooting and Alignment
Remove the signal lead from the sound IF module, as this eliminates background noise, and turn the volume up to full level. Refer to the IF and audio circuits in Fig. 20. A clip lead from the 0.1 uF test capacitor to the collector of the sound output transistor, (TR15), should produce a very weak 60 Hz hum.
At the base of TR15, a louder hum, should be detected if the audio output transistor is amplifying properly.
Fig. 20. Audio IF and sound output circuits.
At the collector of sound driver (TR14), you should find the same hum level.
At the base of TR14, there should be a louder signal, and the volume control will have no effect.
At the lead from the IF module, the same sound level as above should be heard, but the volume control will affect the sound output.
Now reconnect the sound IF lead, if the audio amplifier circuit has been found to be good.
Sound Alignment
Remove the sound IF and ratio detector module from the main chassis and keep the cover in place.
Now perform an alignment at 4.5 MHz. Insert 24 volts B+. Insert a 4.5 MHz carrier modulated with an audio tone.
Next check for response and audio limiting.
Apply 4.5 MHz unmodulated carrier at the input. Connect VTVM for DC measurement at audio IF output lead, disconnected from the audio circuit. Adjust the frequency a maximum of ±50 kHz either side of the 4.5 MHz center frequency. The meter should be observed to have linear swing of the output voltage with frequency change.
Shift the frequency, on a strong signal, so that the output voltage reads +1 volt DC. Now adjusting the input voltage from 100 mV down to 20 mV should produce no change in the meter reading. This tests limiting and sensitivity. If the 4.5 MHz carrier does not produce DC voltage swing, remove the case cover, which will detune the 4.5 MHz circuitry. Inspect the chassis for any obvious damage.
Check DC continuity at the output circuitry. Inspect T4, and the ratio detector output load.
See if the diodes are shorted. Check front to back ratio.
Connect 24 volt B+ and check for voltages as shown on the circuit diagram.
Circuit Operation
Briefly, limiting action in the ratio detector is accomplished partly by having equal DC voltage developed across each half of the L16C secondary transformer winding, across R48 and R49, and partly due to the electrolytic capacitor C73.
The 680 ohm resistors are primarily to offset variations in forward resistance of the matched diode pair (X5 and X6). Although the diode pairs are "matched" one may have a forward resistance of 20 ohms, the other somewhat different. However, the 680 ohms insures that the detecting and limiting action is not impaired.